From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 20:05:10 +0000 (-0700)
Subject: Add init support
X-Git-Tag: working-ls180~1085^2~86
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5ce0c31d0e01603264b23cff8f6d431902f08b63;p=yosys.git

Add init support
---

diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc
index bfda55af0..7240c2fa3 100644
--- a/passes/pmgen/xilinx_srl.cc
+++ b/passes/pmgen/xilinx_srl.cc
@@ -42,20 +42,29 @@ void reduce_chain(xilinx_srl_pm &pm, int minlen)
 
 	auto last_cell = ud.longest_chain.back();
 
+	SigSpec initval;
 	for (auto cell : ud.longest_chain) {
 		log_debug("    %s\n", log_id(cell));
+		SigBit Q = cell->getPort(ID(Q));
+		log_assert(Q.wire);
+		auto it = Q.wire->attributes.find(ID(init));
+		if (it != Q.wire->attributes.end()) {
+			initval.append(it->second[Q.offset]);
+		}
+		else
+			initval.append(State::Sx);
 		if (cell != last_cell)
 			pm.autoremove(cell);
 	}
 
 	Cell *c = last_cell;
-	SigSpec Q = st.first->getPort(ID(Q));
+	SigBit Q = st.first->getPort(ID(Q));
 	c->setPort(ID(Q), Q);
 
 	if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
 		c->parameters.clear();
 		c->setParam(ID(DEPTH), GetSize(ud.longest_chain));
-		// TODO c->setParam(ID(INIT), init);
+		c->setParam(ID(INIT), initval.as_const());
 		if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
 			c->setParam(ID(CLKPOL), 1);
 		else
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7ba67409b..49f32002c 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -406,7 +406,7 @@ struct SynthXilinxPass : public ScriptPass
 			// This shregmap call infers fixed length shift registers after abc
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
-				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
+				run("xilinx_srl -minlen 3", "(skip if '-nosrl')");
 			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
 			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");