From: Luke Kenneth Casson Leighton Date: Sat, 4 Apr 2020 15:45:32 +0000 (+0100) Subject: replace if RA = 0 then b<-0 etc. with b<-(RA|0) X-Git-Tag: convert-csv-opcode-to-binary~2964 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5ce2f7b7277b1f21a77ca2f78238069d4d463599;p=libreriscv.git replace if RA = 0 then b<-0 etc. with b<-(RA|0) --- diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn index 2ba81d190..3565461ad 100644 --- a/openpower/isa/fixedload.mdwn +++ b/openpower/isa/fixedload.mdwn @@ -4,8 +4,7 @@ D-Form * lbz RT,D(RA) - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + EXTS(D) RT <- [0]*56 || MEM(EA, 1) @@ -19,8 +18,7 @@ X-Form * lbzx RT,RA,RB - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + (RB) RT <- [0] * 56 || MEM(EA, 1) @@ -62,8 +60,7 @@ D-Form * lhz RT,D(RA) - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + EXTS(D) RT <- [0] * 48 || MEM(EA, 2) @@ -77,8 +74,7 @@ X-Form * lhzx RT,RA,RB - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + (RB) RT <- [0] * 48 || MEM(EA, 2) @@ -120,8 +116,7 @@ D-Form * lha RT,D(RA) - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + EXTS(D) RT <- EXTS(MEM(EA, 2)) @@ -135,8 +130,7 @@ X-Form * lhax RT,RA,RB - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + (RB) RT <- EXTS(MEM(EA, 2)) @@ -178,8 +172,7 @@ D-Form * lwz RT,D(RA) - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + EXTS(D) RT <- [0] * 32 || MEM(EA, 4) @@ -193,8 +186,7 @@ X-Form * lwzx RT,RA,RB - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + (RB) RT <- [0] * 32 || MEM(EA, 4) @@ -236,8 +228,7 @@ D-Form * lwa RT,DS(RA) - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + EXTS(DS || 0b00) RT <- EXTS(MEM(EA, 4)) @@ -251,8 +242,7 @@ X-Form * lwax RT,RA,RB - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + (RB) RT <- EXTS(MEM(EA, 4)) @@ -280,8 +270,7 @@ DS-Form * ld RT,DS(RA) - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + EXTS(DS || 0b00) RT <- MEM(EA, 8) @@ -295,8 +284,7 @@ X-Form * ldx RT,RA,RB - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + (RB) RT <- MEM(EA, 8) @@ -338,8 +326,7 @@ DQ-Form * lq RTp,DQ(RA) - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + EXTS(DQ || 0b0000) RTp <- MEM(EA, 16) @@ -353,8 +340,7 @@ X-Form * lhbrx RT,RA,RB - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + (RB) load_data <- MEM(EA, 2) RT <- [0]*48 || load_data[8:15] || load_data[0:7] @@ -369,8 +355,7 @@ X-Form * lwbrx RT,RA,RB - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + (RB) load_data <- MEM(EA, 4) RT <- [0] * 32 || load_data[24:31] || load_data[16:23] @@ -386,8 +371,7 @@ X-Form * ldbrx RT,RA,RB - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + (RB) load_data <- MEM(EA, 8) RT <- load_data[56:63] || load_data[48:55] @@ -405,8 +389,7 @@ DQ-Form * lmw RT,D(RA) - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + EXTS(D) r <- RT do while r <= 31 diff --git a/openpower/isa/fixedstore.mdwn b/openpower/isa/fixedstore.mdwn index 5a578558d..314d71823 100644 --- a/openpower/isa/fixedstore.mdwn +++ b/openpower/isa/fixedstore.mdwn @@ -4,8 +4,7 @@ D-Form * stb RS,D(RA) - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + EXTS(D) MEM(EA, 1) <- (RS)[56:63] @@ -19,8 +18,7 @@ X-Form * stbx RS,RA,RB - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + (RB) MEM(EA, 1) <- (RS)[56:63] @@ -62,8 +60,7 @@ D-Form * sth RS,D(RA) - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + EXTS(D) MEM(EA, 2) <- (RS)[48:63] @@ -77,8 +74,7 @@ X-Form * sthx RS,RA,RB - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + (RB) MEM(EA, 2) <- (RS)[48:63] @@ -120,8 +116,7 @@ D-Form * stw RS,D(RA) - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + EXTS(D) MEM(EA, 4) <- (RS)[32:63] @@ -135,8 +130,7 @@ X-Form * stwx RS,RA,RB - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + (RB) MEM(EA, 4) <- (RS)[32:63] @@ -178,8 +172,7 @@ DS-Form * std RS,DS(RA) - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + EXTS(DS || 0b00) MEM(EA, 8) <- (RS) @@ -193,8 +186,7 @@ X-Form * stdx RS,RA,RB - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + (RB) MEM(EA, 8) <- (RS) @@ -236,8 +228,7 @@ DS-Form * stq RSp,DS(RA) - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + EXTS(DS || 0b00) MEM(EA, 16) <- RSp @@ -251,8 +242,7 @@ X-Form * sthbrx RS,RA,RB - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + (RB) MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55] @@ -266,8 +256,7 @@ X-Form * stwbrx RS,RA,RB - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + (RB) MEM(EA, 4) <- (RS)[56:63] || (RS)[48:55] || (RS)[40:47] ||(RS)[32:39] @@ -282,8 +271,7 @@ X-Form * stdbrx RS,RA,RB - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + (RB) MEM(EA, 8) <- (RS) [56:63] || (RS)48:55] || (RS)[40:47] || (RS)[32:39] @@ -300,8 +288,7 @@ D-Form * stmw RS,D(RA) - if RA = 0 then b <- 0 - else b <- (RA) + b <- (RA|0) EA <- b + EXTS(D) r <- RS do while r <= 31