From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Thu, 21 Oct 2021 16:26:47 +0000 (+0200)
Subject: Change implicit conversions from bool to Sig* to explicit.
X-Git-Tag: yosys-0.11~30
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5cebf6a8efb4f1e9b836db76be0bb2a964932905;p=yosys.git

Change implicit conversions from bool to Sig* to explicit.

Also fixes some completely broken code in extract_reduce.
---

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index e072d5bd1..96982d2d9 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -756,7 +756,7 @@ struct RTLIL::SigBit
 
 	SigBit();
 	SigBit(RTLIL::State bit);
-	SigBit(bool bit);
+	explicit SigBit(bool bit);
 	SigBit(RTLIL::Wire *wire);
 	SigBit(RTLIL::Wire *wire, int offset);
 	SigBit(const RTLIL::SigChunk &chunk);
@@ -838,7 +838,7 @@ public:
 	SigSpec(const std::vector<RTLIL::SigBit> &bits);
 	SigSpec(const pool<RTLIL::SigBit> &bits);
 	SigSpec(const std::set<RTLIL::SigBit> &bits);
-	SigSpec(bool bit);
+	explicit SigSpec(bool bit);
 
 	SigSpec(RTLIL::SigSpec &&other) {
 		width_ = other.width_;
diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc
index b2da126ab..892e9a364 100644
--- a/passes/techmap/extract_reduce.cc
+++ b/passes/techmap/extract_reduce.cc
@@ -152,10 +152,10 @@ struct ExtractReducePass : public Pass
 						log_assert(y.size() == 1);
 
 						// Should only continue if there is one fanout back into a cell (not to a port)
-						if (sig_to_sink[y[0]].size() != 1)
+						if (sig_to_sink[y].size() != 1 || port_sigs.count(y))
 							break;
 
-						x = *sig_to_sink[y[0]].begin();
+						x = *sig_to_sink[y].begin();
 					}
 
 					sinks.insert(head_cell);
@@ -183,13 +183,15 @@ struct ExtractReducePass : public Pass
 								continue;
 							}
 
+							auto xy = sigmap(x->getPort(ID::Y));
+
 							//If this signal drives a port, add it to the sinks
 							//(even though it may not be the end of a chain)
-							if(port_sigs.count(x) && !consumed_cells.count(x))
+							if(port_sigs.count(xy) && !consumed_cells.count(x))
 								sinks.insert(x);
 
 							//It's a match, search everything out from it
-							auto& next = sig_to_sink[x];
+							auto& next = sig_to_sink[xy];
 							for(auto z : next)
 								next_loads.insert(z);
 						}