From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 3 Jun 2020 21:45:12 +0000 (+0100)
Subject: link up PriorityPickers on read channels
X-Git-Tag: div_pipeline~626
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5d081abfa207a1f1edb708f6c6698df225df6476;p=soc.git

link up PriorityPickers on read channels
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index d34dfef2..a8b3b33e 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -7,6 +7,8 @@ Function Unit to be operational.
 from nmigen import Elaboratable, Module, Signal
 from nmigen.cli import rtlil
 
+from nmutil.picker import PriorityPicker
+
 from soc.fu.compunits.compunits import AllFunctionUnits
 from soc.regfile.regfiles import RegFiles
 from soc.decoder.power_decoder import create_pdecode
@@ -31,6 +33,12 @@ class NonProductionCore(Elaboratable):
         regs = self.regs
         fus = self.fus.fus
 
+        # enable-signals for each FU, get one bit for each FU (by name)
+        fu_enable = Signal(len(fus), reset_less=True)
+        fu_bitdict = {}
+        for i, funame in enumerate(fus.keys()):
+            fu_bitdict[funame] = fu_enable[i]
+
         # dictionary of lists of regfile read ports
         byregfiles_rd = {}
         byregfiles_rdspec = {}
@@ -57,9 +65,23 @@ class NonProductionCore(Elaboratable):
                 (regname, rdflag, read, wid) = byregfiles_rdspec[regfile]
                 print ("  %s" % regname, wid, read, rdflag)
                 for (funame, fu) in fuspec:
-                    print ("    ", funame, fu)
+                    print ("    ", funame, fu, fu.src_i[idx])
                     print ()
 
+        # okaay, now we need a PriorityPicker per regfile per regfile port
+        # loootta pickers... peter piper picked a pack of pickled peppers...
+        rdpickers = {}
+        for regfile, spec in byregfiles_rd.items():
+            rdpickers[regfile] = {}
+            for idx, fuspec in spec.items():
+                rdpickers[regfile][idx] = rdpick = PriorityPicker(len(fuspec))
+                setattr(m.submodules, "rdpick_%s_%d" % (regfile, idx), rdpick)
+                for pi, (funame, fu) in enumerate(fuspec):
+                    # connect request-read to picker input, and output to go-rd
+                    fu_active = fu_bitdict[funame]
+                    comb += rdpick.i[pi].eq(fu.rd_rel_o[idx] & fu_active)
+                    comb += fu.go_rd_i[idx].eq(rdpick.o[pi])
+
         return m
 
     def __iter__(self):