From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 18:47:06 +0000 (-0700)
Subject: techmap before read
X-Git-Tag: working-ls180~1075^2^2~38
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5d0f6cbd540e1be4525563329dabd2f2aaf7069e;p=yosys.git

techmap before read
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 263788fec..218192315 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -390,8 +390,8 @@ struct SynthXilinxPass : public ScriptPass
 			else if (abc9) {
 				if (family != "xc7")
 					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
-				run("read_verilog -icells -lib +/xilinx/abc_model.v");
 				run("techmap -map +/xilinx/abc_map.v -max_iter 1");
+				run("read_verilog -icells -lib +/xilinx/abc_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 				else