From: lkcl <lkcl@web>
Date: Wed, 18 Aug 2021 12:02:36 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~397
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5d1289ec213b6c345a93bd83fa929398ef93e47e;p=libreriscv.git

---

diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn
index 002eede7e..8e9d20229 100644
--- a/openpower/sv/sprs.mdwn
+++ b/openpower/sv/sprs.mdwn
@@ -73,6 +73,11 @@ full context save/restore (see SVSRR0).  It contains (and permits setting of):
 * hphint - Horizontal Parallelism Hint. In Vertical First Mode
    hardware **MAY** perform up to this many elements in parallel
    per instruction. Set to zero to indicate "no hint".
+* SVme - REMAP enable bits, indicating which register is to be
+ REMAPed.  RA, RB, RC, RT or EA.
+* mi0-mi4 - when the corresponding SVme bit is enabled, mi0-mi4
+  indicate the SVSHAPE (0-3) that the corresponding register (RA etc)
+  should use.
 
 For hphint, the number chosen must be consistently
 executed **every time**. Hardware is not permitted to execute five