From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 17 Jun 2020 14:24:27 +0000 (+0100)
Subject: comment ISACaller setup
X-Git-Tag: div_pipeline~342
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5d183e9ed2beef48bab5166139d3385d948b43b4;p=soc.git

comment ISACaller setup
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 504ab94a..ec6af39c 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -240,12 +240,14 @@ class ISACaller:
             for i, code in enumerate(disassembly):
                 self.disassembly[i*4 + self.fake_pc] = code
 
+        # set up registers, instruction memory, data memory, PC, SPRs, MSR
         self.gpr = GPR(decoder2, regfile)
         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
         self.pc = PC()
         self.spr = SPR(decoder2, initial_sprs)
         self.msr = SelectableInt(initial_msr, 64) # underlying reg
+
         # TODO, needed here:
         # FPR (same as GPR except for FP nums)
         # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)