From: Megan Wachs <megan@sifive.com>
Date: Fri, 22 Sep 2017 20:55:55 +0000 (-0700)
Subject: signal_bundles: add missing file
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5d1e9b793a0fd910abe4dbbf79c63cb51b0bc8df;p=sifive-blocks.git

signal_bundles: add missing file
---

diff --git a/src/main/scala/devices/pwm/PWMPins.scala b/src/main/scala/devices/pwm/PWMPins.scala
new file mode 100644
index 0000000..7ab76f0
--- /dev/null
+++ b/src/main/scala/devices/pwm/PWMPins.scala
@@ -0,0 +1,27 @@
+// See LICENSE for license details.
+package sifive.blocks.devices.pwm
+
+import Chisel._
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.util.HeterogeneousBag
+import sifive.blocks.devices.pinctrl.{Pin}
+
+class PWMSignals[T <: Data] (pingen: ()=> T, val c: PWMParams) extends Bundle {
+
+  val pwm: Vec[T] = Vec(c.ncmp, pingen())
+
+  override def cloneType: this.type =
+    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
+}
+
+class PWMPins[T <: Pin] (pingen: ()=> T, c: PWMParams) extends PWMSignals[T](pingen, c)
+
+object PWMPinsFromPort {
+  def apply[T <: Pin] (pins: PWMSignals[T], port: PWMPortIO): Unit = {
+    (pins.pwm zip port.port)  foreach {case (pin, port) =>
+      pin.outputPin(port)
+    }
+  }
+}