From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 29 Sep 2018 03:19:19 +0000 (+0100)
Subject: add stub for SV REG configs
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5d443b20afd32d4d82d0285290f39ebdb061cda9;p=riscv-isa-sim.git

add stub for SV REG configs
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 83c6439..71b030b 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -346,6 +346,15 @@ void processor_t::set_csr(int which, reg_t val)
       state.vl = std::min(state.mvl, state.XPR[val]);
       state.XPR.write(val, state.vl);
       break;
+    case CSR_SVREGCFG0:
+    case CSR_SVREGCFG1:
+    case CSR_SVREGCFG2:
+    case CSR_SVREGCFG3:
+    case CSR_SVREGCFG4:
+    case CSR_SVREGCFG5:
+    case CSR_SVREGCFG6:
+    case CSR_SVREGCFG7:
+      break;
 #endif
     case CSR_FFLAGS:
       dirty_fp_state;