From: Ciro Santilli <ciro.santilli@arm.com> Date: Thu, 15 Oct 2020 13:31:46 +0000 (+0100) Subject: arch-arm: serialize miscregs as a map X-Git-Tag: develop-gem5-snapshot~424 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5d47dbff41c37897cc3111ceae1275e75aafc195;p=gem5.git arch-arm: serialize miscregs as a map This will prevent checkpoints from breaking on every miscreg addition. Before this commit, miscregs were stored as an array: [system.cpu.isa] miscRegs=965 0 0 0 0 0 0 0 0 0 0 0 17895697 ... and after this commit they are stored as a map: [system.cpu.isa] [system.cpu.isa.miscRegs] cpsr=965 spsr=0 spsr_fiq=0 spsr_irq=0 spsr_svc=0 spsr_mon=0 spsr_abt=0 spsr_hyp=0 spsr_und=0 elr_hyp=0 fpsid=0 fpscr=0 mvfr1=17895697 JIRA: https://gem5.atlassian.net/browse/GEM5-661 Change-Id: I49999c7206bd9ac1cfb81297d45c8117ff8ae675 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36116 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Richard Cooper <richard.cooper@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> --- diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 9b1cde31f..9b0b9577c 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -2354,14 +2354,14 @@ void ISA::serialize(CheckpointOut &cp) const { DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n"); - SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS); + SERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS); } void ISA::unserialize(CheckpointIn &cp) { DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n"); - UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS); + UNSERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS); CPSR tmp_cpsr = miscRegs[MISCREG_CPSR]; updateRegMap(tmp_cpsr); }