From: Ivan Grokhotkov <ivan@espressif.com>
Date: Mon, 8 Jun 2020 21:06:11 +0000 (+0200)
Subject: [breaking-change] resources: distinguish "dte"/"dce" roles of UART.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5d56f7fd584a52f0c5498aa5b8f64c23c805205b;p=nmigen-boards.git

[breaking-change] resources: distinguish "dte"/"dce" roles of UART.

UARTResource gets a new argument, "role", which determines flow
control signal directions:
- DCE means that the design acts as a modem
- DTE means that the design acts as a PC
---

diff --git a/nmigen_boards/resources/interface.py b/nmigen_boards/resources/interface.py
index 655faf6..97489e2 100644
--- a/nmigen_boards/resources/interface.py
+++ b/nmigen_boards/resources/interface.py
@@ -5,22 +5,30 @@ __all__ = ["UARTResource", "IrDAResource", "SPIResource"]
 
 
 def UARTResource(*args, rx, tx, rts=None, cts=None, dtr=None, dsr=None, dcd=None, ri=None,
-                 conn=None, attrs=None):
+                 conn=None, attrs=None, role=None):
+    assert role in ("dce", "dte")
+    if role == "dte":
+        dce_to_dte = "i"
+        dte_to_dce = "o"
+    else:
+        dce_to_dte = "o"
+        dte_to_dce = "i"
+
     io = []
     io.append(Subsignal("rx", Pins(rx, dir="i", conn=conn, assert_width=1)))
     io.append(Subsignal("tx", Pins(tx, dir="o", conn=conn, assert_width=1)))
     if rts is not None:
-        io.append(Subsignal("rts", Pins(rts, dir="o", conn=conn, assert_width=1)))
+        io.append(Subsignal("rts", Pins(rts, dir=dte_to_dce, conn=conn, assert_width=1)))
     if cts is not None:
-        io.append(Subsignal("cts", Pins(cts, dir="i", conn=conn, assert_width=1)))
+        io.append(Subsignal("cts", Pins(cts, dir=dce_to_dte, conn=conn, assert_width=1)))
     if dtr is not None:
-        io.append(Subsignal("dtr", Pins(dtr, dir="o", conn=conn, assert_width=1)))
+        io.append(Subsignal("dtr", Pins(dtr, dir=dte_to_dce, conn=conn, assert_width=1)))
     if dsr is not None:
-        io.append(Subsignal("dsr", Pins(dsr, dir="i", conn=conn, assert_width=1)))
+        io.append(Subsignal("dsr", Pins(dsr, dir=dce_to_dte, conn=conn, assert_width=1)))
     if dcd is not None:
-        io.append(Subsignal("dcd", Pins(dcd, dir="i", conn=conn, assert_width=1)))
+        io.append(Subsignal("dcd", Pins(dcd, dir=dce_to_dte, conn=conn, assert_width=1)))
     if ri is not None:
-        io.append(Subsignal("ri", Pins(ri, dir="i", conn=conn, assert_width=1)))
+        io.append(Subsignal("ri", Pins(ri, dir=dce_to_dte, conn=conn, assert_width=1)))
     if attrs is not None:
         io.append(attrs)
     return Resource.family(*args, default_name="uart", ios=io)