From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 28 Mar 2022 11:27:38 +0000 (+0100)
Subject: extend cs in hyperram to multiple bits
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5d60fbbaadac424f1796809797256b57b5b82b86;p=lambdasoc.git

extend cs in hyperram to multiple bits
---

diff --git a/lambdasoc/periph/hyperram.py b/lambdasoc/periph/hyperram.py
index c9b5d94..3527ee4 100644
--- a/lambdasoc/periph/hyperram.py
+++ b/lambdasoc/periph/hyperram.py
@@ -46,7 +46,7 @@ class HyperRAMASICPhy(Elaboratable):
     def __init__(self, io):
         self.io = io
         self.ck = ck = Signal()
-        self.cs  = cs = Signal()
+        self.cs  = cs = Signal(len(self.io.cs_n))
         self.rst_n = rst_n = Signal()
 
         self.dq_o  = dq_o  = Signal(8)
@@ -65,7 +65,7 @@ class HyperRAMASICPhy(Elaboratable):
 
         comb += [
             self.io["rwds_o"].eq(rwds_o),
-            self.io["csn_o"].eq(~cs),
+            self.io["cs_n"].eq(~cs),
             self.io["csn_oe"].eq(0),
             self.io["ck_o"].eq(ck),
             self.io["ck_oe"].eq(0),
@@ -91,10 +91,10 @@ class HyperRAMASICPhy(Elaboratable):
 #   dut = HyperRAM(io=HyperRamPads(), phy_kls=TestHyperRAMPHY)
 
 class HyperRAMPads:
-    def __init__(self, dw=8):
+    def __init__(self, dw=8, n_cs=1):
         self.rst_n = Signal()
         self.ck  = Signal()
-        self.cs_n = Signal()
+        self.cs_n = Signal(n_cs)
         self.dq   = Record([("oe", 1), ("o", dw),     ("i", dw)])
         self.rwds = Record([("oe", 1), ("o", dw//8),  ("i", dw//8)])
         self.dq.o.name = "dq_o"
@@ -113,7 +113,7 @@ class HyperRAMPHY(Elaboratable):
     def __init__(self, pads):
         self.pads = pads
         self.ck = pads.ck
-        self.cs = Signal()
+        self.cs = Signal(len(self.pads.cs_n))
         self.rst_n = pads.rst_n
         self.dq_o = pads.dq.o
         self.dq_i = pads.dq.i
@@ -143,9 +143,12 @@ class HyperRAM(Peripheral, Elaboratable):
 
     This core favors portability and ease of use over performance.
     Tested: Winbond W956D8MBYA latency=7
+    Cypress S27KL0641DABHI020 requires latency=6
     """
-    def __init__(self, *, io, phy_kls, latency=6, bus=None,
-                                       features=frozenset()):
+    def __init__(self, *, io, phy_kls,
+                          latency=6,
+                          addr_width=23, # 8 GBytes, per IC
+                          bus=None, features=frozenset()):
         super().__init__()
         self.io = io
         self.phy = phy_kls(io)
@@ -322,7 +325,7 @@ class HyperRAM(Peripheral, Elaboratable):
 
 if __name__ == '__main__':
     layout=[('rwds_o', 1), ('rwds_oe', 1),
-            ('csn_o', 1), ('csn_oe', 1),
+            ('cs_n', 1), ('csn_oe', 1),
             ('ck_o', 1), ('ck_oe', 1),
             ('rst_n', 1)]
     for i in range(8):