From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 3 Oct 2019 17:30:33 +0000 (-0700)
Subject: Use equiv_opt -async2sync for xilinx
X-Git-Tag: working-ls180~1001^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5d680590d6bccd929ed3909248dbb73fb3876e65;p=yosys.git

Use equiv_opt -async2sync for xilinx
---

diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index ac1102896..bd1dffd21 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -2,9 +2,7 @@ read_verilog latches.v
 
 proc
 flatten
-equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-async2sync
-equiv_opt -assert -run prove: -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 
 design -load preopt
 synth_xilinx