From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Jun 2020 23:36:37 +0000 (+0100)
Subject: add links
X-Git-Tag: convert-csv-opcode-to-binary~2520
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5d70ca780304f2e1db2318f3f509535a44966297;p=libreriscv.git

add links
---

diff --git a/3d_gpu/simple_core.mdwn b/3d_gpu/simple_core.mdwn
index af84e0179..fd79bd2c3 100644
--- a/3d_gpu/simple_core.mdwn
+++ b/3d_gpu/simple_core.mdwn
@@ -1,3 +1,5 @@
+# Non-production Simple POWER9 Core
+
 the simple core is taking shape as a combination of all the pipelines,
 connected to the (5) types of register files.  all unit tests that
 have been developed to test *individual* pipelines have been borrowed
@@ -58,3 +60,8 @@ the next phases will involve:
 at that point we will have an actual core that is capable of executing
 instructions on its own.  further code-morphs can then take place including
 adding in the [[architecture/6600scoreboard]].
+
+# Links
+
+* <https://bugs.libre-soc.org/show_bug.cgi?id=346>
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/007828.html>