From: lkcl <lkcl@web>
Date: Fri, 8 Jan 2021 14:29:58 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~552
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5d8a205ba9606c47fa6dbf39ebf4bbe9481456b5;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 457d96ded..d6455051e 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -34,8 +34,6 @@ At the minimum however it is possible to provide unit stride and vector mode, as
     # LD not VLD!
     # op_width: lb=1, lh=2, lw=4, ld=8
     op_load(RT, RA, op_width, immed, svctx, update):
-      rdv = map_dest_extra(RT); # possible REMAP
-      rsv = map_src_extra(RA);  # possible REMAP
       ps = get_pred_val(FALSE, RA); # predication on src
       pd = get_pred_val(FALSE, RT); # ... AND on dest
       for (int i = 0, int j = 0; i < VL && j < VL;):
@@ -62,7 +60,7 @@ At the minimum however it is possible to provide unit stride and vector mode, as
         EA = srcbase + offs
         # update RA? load from memory
         if update: ireg[rsv+i] = EA;
-        ireg[rdv+j] <= MEM[EA];
+        ireg[RT+j] <= MEM[EA];
         if (!RT.isvec)
             break # destination scalar, end now
         if (RA.isvec) i++;