From: Luke Kenneth Casson Leighton Date: Sun, 31 Jan 2021 20:42:29 +0000 (+0000) Subject: start an ISACaller SVP64 unit test X-Git-Tag: convert-csv-opcode-to-binary~272 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5d91d698a990e8bb6c32896adac3ae8f59de027f;p=soc.git start an ISACaller SVP64 unit test --- diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py index 998f611b..684b38aa 100644 --- a/src/soc/decoder/isa/test_caller.py +++ b/src/soc/decoder/isa/test_caller.py @@ -16,59 +16,59 @@ class Register: def __init__(self, num): self.num = num +def run_tst(generator, initial_regs, initial_sprs={}): + m = Module() + comb = m.d.comb + instruction = Signal(32) + + pdecode = create_pdecode() + + gen = list(generator.generate_instructions()) + insncode = generator.assembly.splitlines() + instructions = list(zip(gen, insncode)) + + m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) + simulator = ISA(pdecode2, initial_regs, initial_sprs, 0, + initial_insns=gen, respect_pc=True, + disassembly=insncode, + bigendian=0) + comb += pdecode2.dec.raw_opcode_in.eq(instruction) + sim = Simulator(m) + + + def process(): + + pc = simulator.pc.CIA.value + index = pc//4 + while index < len(instructions): + print("instr pc", pc) + try: + yield from simulator.setup_one() + except KeyError: # indicates instruction not in imem: stop + break + yield Settle() + + ins, code = instructions[index] + print("0x{:X}".format(ins & 0xffffffff)) + print(code) + + # ask the decoder to decode this binary data (endian'd) + yield pdecode2.dec.bigendian.eq(0) # little / big? + yield instruction.eq(ins) # raw binary instr. + yield Delay(1e-6) + opname = code.split(' ')[0] + yield from simulator.call(opname) + pc = simulator.pc.CIA.value + index = pc//4 -class DecoderTestCase(FHDLTestCase): - - def run_tst(self, generator, initial_regs, initial_sprs={}): - m = Module() - comb = m.d.comb - instruction = Signal(32) - - pdecode = create_pdecode() - - gen = list(generator.generate_instructions()) - insncode = generator.assembly.splitlines() - instructions = list(zip(gen, insncode)) - - m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) - simulator = ISA(pdecode2, initial_regs, initial_sprs, 0, - initial_insns=gen, respect_pc=True, - disassembly=insncode, - bigendian=0) - comb += pdecode2.dec.raw_opcode_in.eq(instruction) - sim = Simulator(m) - + sim.add_process(process) + with sim.write_vcd("simulator.vcd", "simulator.gtkw", + traces=[]): + sim.run() + return simulator - def process(): - pc = simulator.pc.CIA.value - index = pc//4 - while index < len(instructions): - print("instr pc", pc) - try: - yield from simulator.setup_one() - except KeyError: # indicates instruction not in imem: stop - break - yield Settle() - - ins, code = instructions[index] - print("0x{:X}".format(ins & 0xffffffff)) - print(code) - - # ask the decoder to decode this binary data (endian'd) - yield pdecode2.dec.bigendian.eq(0) # little / big? - yield instruction.eq(ins) # raw binary instr. - yield Delay(1e-6) - opname = code.split(' ')[0] - yield from simulator.call(opname) - pc = simulator.pc.CIA.value - index = pc//4 - - sim.add_process(process) - with sim.write_vcd("simulator.vcd", "simulator.gtkw", - traces=[]): - sim.run() - return simulator +class DecoderTestCase(FHDLTestCase): def test_add(self): lst = ["add 1, 3, 2"] @@ -316,7 +316,7 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.cr, SelectableInt(expected << ((7-i)*4), 32)) def run_tst_program(self, prog, initial_regs=[0] * 32): - simulator = self.run_tst(prog, initial_regs) + simulator = run_tst(prog, initial_regs) simulator.gpr.dump() return simulator diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py new file mode 100644 index 00000000..c9d1391a --- /dev/null +++ b/src/soc/decoder/isa/test_caller_svp64.py @@ -0,0 +1,39 @@ +from nmigen import Module, Signal +from nmigen.back.pysim import Simulator, Delay, Settle +from nmutil.formaltest import FHDLTestCase +import unittest +from soc.decoder.isa.caller import ISACaller +from soc.decoder.power_decoder import (create_pdecode) +from soc.decoder.power_decoder2 import (PowerDecode2) +from soc.simulator.program import Program +from soc.decoder.isa.caller import ISACaller, inject +from soc.decoder.selectable_int import SelectableInt +from soc.decoder.orderedset import OrderedSet +from soc.decoder.isa.all import ISA +from soc.decoder.isa.test_caller import Register, run_tst +from soc.sv.trans.svp64 import SVP64Asm + + +class DecoderTestCase(FHDLTestCase): + + def test_sv_add(self): + isa = SVP64Asm(['sv.add 1, 2, 3' + ]) + + lst = list(isa) + print ("listing", lst) + initial_regs = [0] * 32 + initial_regs[3] = 0x1234 + initial_regs[2] = 0x4321 + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_regs) + self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64)) + + def run_tst_program(self, prog, initial_regs=[0] * 32): + simulator = run_tst(prog, initial_regs) + simulator.gpr.dump() + return simulator + + +if __name__ == "__main__": + unittest.main() diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py index 746fa563..4c3b88af 100644 --- a/src/soc/sv/trans/svp64.py +++ b/src/soc/sv/trans/svp64.py @@ -112,7 +112,7 @@ def decode_ffirst(encoding): # decodes svp64 assembly listings and creates EXT001 svp64 prefixes -class SVP64: +class SVP64Asm: def __init__(self, lst): self.lst = lst self.trans = self.translate(lst) @@ -543,7 +543,7 @@ class SVP64: return res if __name__ == '__main__': - isa = SVP64(['slw 3, 1, 4', + isa = SVP64Asm(['slw 3, 1, 4', 'extsw 5, 3', 'sv.extsw 5, 3', 'sv.cmpi 5, 1, 3, 2', @@ -556,4 +556,5 @@ if __name__ == '__main__': 'sv.extsw./satu/sz/dz/sm=r3/m=r3 5, 31', 'sv.extsw./pr=eq 5.v, 31', ]) + print ("list", list(isa)) csvs = SVP64RM()