From: lkcl <lkcl@web>
Date: Thu, 21 Apr 2022 14:55:44 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2644
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5d9673196fab1e062ccf849532f658a39db2a9dc;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn
index 42a08c5a5..85b8e1ac1 100644
--- a/openpower/sv/biginteger/analysis.mdwn
+++ b/openpower/sv/biginteger/analysis.mdwn
@@ -165,7 +165,7 @@ purpose of letting it be added onto the next BigInt digit.
 
 Successive iterations thus effectively use RC as a 64-bit carry, and
 as noted by Intel in their notes on mulx,
-RA*RB+RC+RD cannot overflow, so does not require
+`RA*RB+RC+RD` cannot overflow, so does not require
 setting an additional CA flag. We first cover the chain of
 RA*RB+RC as follows: