From: Luke Kenneth Casson Leighton Date: Fri, 7 Jun 2019 22:17:52 +0000 (+0100) Subject: rename fu-regs rd/wr sel vector X-Git-Tag: div_pipeline~1884 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5d9f1eab12603ad0f9ce654b114cde087c199ac0;p=soc.git rename fu-regs rd/wr sel vector --- diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index 212653b1..456bb3eb 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -286,11 +286,11 @@ class FunctionUnits(Elaboratable): intregdeps = FURegDepMatrix(n_intfus, self.n_regs) m.submodules.intregdeps = intregdeps - comb += self.g_int_rd_pend_o.eq(intregdeps.rd_rsel_o) - comb += self.g_int_wr_pend_o.eq(intregdeps.wr_rsel_o) + comb += self.g_int_rd_pend_o.eq(intregdeps.v_rd_rsel_o) + comb += self.g_int_wr_pend_o.eq(intregdeps.v_wr_rsel_o) - comb += intregdeps.rd_pend_i.eq(intregdeps.rd_rsel_o) - comb += intregdeps.wr_pend_i.eq(intregdeps.wr_rsel_o) + comb += intregdeps.rd_pend_i.eq(intregdeps.v_rd_rsel_o) + comb += intregdeps.wr_pend_i.eq(intregdeps.v_wr_rsel_o) comb += intfudeps.rd_pend_i.eq(intregdeps.rd_pend_o) comb += intfudeps.wr_pend_i.eq(intregdeps.wr_pend_o) diff --git a/src/scoreboard/fu_reg_matrix.py b/src/scoreboard/fu_reg_matrix.py index 72b0ba4d..90ff219d 100644 --- a/src/scoreboard/fu_reg_matrix.py +++ b/src/scoreboard/fu_reg_matrix.py @@ -38,8 +38,8 @@ class FURegDepMatrix(Elaboratable): # Register "Global" vectors for determining RaW and WaR hazards self.wr_pend_i = Signal(n_reg_col, reset_less=True) # wr pending (top) self.rd_pend_i = Signal(n_reg_col, reset_less=True) # rd pending (top) - self.wr_rsel_o = Signal(n_reg_col, reset_less=True) # wr pending (bot) - self.rd_rsel_o = Signal(n_reg_col, reset_less=True) # rd pending (bot) + self.v_wr_rsel_o = Signal(n_reg_col, reset_less=True) # wr pending (bot) + self.v_rd_rsel_o = Signal(n_reg_col, reset_less=True) # rd pending (bot) self.issue_i = Signal(n_fu_row, reset_less=True) # Issue in (top) self.go_wr_i = Signal(n_fu_row, reset_less=True) # Go Write in (left) @@ -173,8 +173,8 @@ class FURegDepMatrix(Elaboratable): m.submodules.rd_v = rd_v m.submodules.wr_v = wr_v - m.d.comb += self.rd_rsel_o.eq(rd_v.g_pend_o) - m.d.comb += self.wr_rsel_o.eq(wr_v.g_pend_o) + m.d.comb += self.v_rd_rsel_o.eq(rd_v.g_pend_o) + m.d.comb += self.v_wr_rsel_o.eq(wr_v.g_pend_o) # --- # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr @@ -214,8 +214,8 @@ class FURegDepMatrix(Elaboratable): yield self.rd_pend_o yield self.wr_pend_i yield self.rd_pend_i - yield self.wr_rsel_o - yield self.rd_rsel_o + yield self.v_wr_rsel_o + yield self.v_rd_rsel_o yield self.rd_src1_pend_o yield self.rd_src2_pend_o