From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 8 Oct 2022 13:29:20 +0000 (+0100)
Subject: drat
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5db40783a86f3df57bfd409742c1de63718c2e03;p=openpower-isa.git

drat
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 65cbb242..c87e7e2a 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -2185,8 +2185,6 @@ class PPCDatabase:
                         for name in insn.names:
                             records[name].add(insn)
                             sections[name] = section
-                            if str(path).endswith("extra.csv"):
-                                print ("extra", name, section)
 
         for (name, multirecord) in sorted(records.items()):
             multirecord = PPCMultiRecord(sorted(multirecord))
@@ -2318,9 +2316,6 @@ class Database:
         self.__db = sorted(db)
         self.__names = dict(sorted(names.items()))
         self.__opcodes = dict(sorted(opcodes.items()))
-        print ("opcodes")
-        for k, v in self.__opcodes.items():
-            print ("    ", bin(k), v)
 
         return super().__init__()
 
@@ -2339,7 +2334,6 @@ class Database:
         # specific hunt for all "extra.csv" matches. TODO: separate db of extras
         if isinstance(key, Instruction):
             ki = int(key)
-            print ("key", bin(ki))
             for k, records in self.__opcodes.items():
                 for record in records:
                     if str(record.section.path).endswith("extra.csv"):
diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index cd70473b..a5dcbe04 100644
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -30,7 +30,7 @@ class SVSTATETestCase(unittest.TestCase):
                                      "'%s' expected '%s'" % (line, expected[i]))
 
 
-    def tst_0_add(self):
+    def test_0_add(self):
         expected = ['addi 1,5,2',
                     'add 1,5,2',
                     'add. 1,5,2',
@@ -39,13 +39,13 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_1_svshape2(self):
+    def test_1_svshape2(self):
         expected = [
                     'svshape2 12,1,15,5,0,0'
                         ]
         self._do_tst(expected)
 
-    def tst_2_d_custom_op(self):
+    def test_2_d_custom_op(self):
         expected = [
                     'fishmv 12,2',
                     'fmvis 12,97',
@@ -53,7 +53,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_3_sv_isel(self):
+    def test_3_sv_isel(self):
         expected = [
                     'sv.isel 12,2,3,33',
                     'sv.isel 12,2,3,*33',
@@ -63,7 +63,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_4_sv_crand(self):
+    def test_4_sv_crand(self):
         expected = [
                     'sv.crand *16,*2,*33',
                     'sv.crand 12,2,33',
@@ -76,21 +76,21 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_5_setvl(self):
+    def test_5_setvl(self):
         expected = [
                     "setvl 5,4,5,0,1,1",
                     "setvl. 5,4,5,0,1,1",
                         ]
         self._do_tst(expected)
 
-    def tst_6_sv_setvl(self):
+    def test_6_sv_setvl(self):
         expected = [
                     "sv.setvl 5,4,5,0,1,1",
                     "sv.setvl 63,35,5,0,1,1",
                         ]
         self._do_tst(expected)
 
-    def tst_7_batch(self):
+    def test_7_batch(self):
         "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25"
         expected = [
                     "addi 2,2,0",
@@ -164,7 +164,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_8_madd(self):
+    def test_8_madd(self):
         expected = [
                     "maddhd 5,4,5,3",
                     "maddhdu 5,4,5,3",
@@ -172,14 +172,14 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_9_fptrans(self):
+    def test_9_fptrans(self):
         "enumerates a list of fptrans instruction disassembly entries"
         db = Database(find_wiki_dir())
         entries = sorted(sv_binutils_fptrans.collect(db))
         dis = lambda entry: sv_binutils_fptrans.dis(entry, binutils=False)
         self._do_tst(list(map(dis, entries)))
 
-    def tst_10_vec(self):
+    def test_10_vec(self):
         expected = [
                     "sv.add./vec2 *3,*7,*11",
                     "sv.add./vec3 *3,*7,*11",
@@ -187,7 +187,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_11_elwidth(self):
+    def test_11_elwidth(self):
         expected = [
                     "sv.add./dw=8 *3,*7,*11",
                     "sv.add./dw=16 *3,*7,*11",
@@ -204,14 +204,14 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_12_sat(self):
+    def test_12_sat(self):
         expected = [
                     "sv.add./satu *3,*7,*11",
                     "sv.add./sats *3,*7,*11",
                         ]
         self._do_tst(expected)
 
-    def tst_12_mr_r(self):
+    def test_12_mr_r(self):
         expected = [
                     "sv.add./mrr/vec2 *3,*7,*11",
                     "sv.add./mr/vec2 *3,*7,*11",
@@ -220,7 +220,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_13_RC1(self):
+    def test_13_RC1(self):
         expected = [
                     "sv.add/ff=RC1 *3,*7,*11",
                     "sv.add/pr=RC1 *3,*7,*11",
@@ -229,7 +229,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_14_rc1_ff_pr(self):
+    def test_14_rc1_ff_pr(self):
         expected = [
                     "sv.add./ff=eq *3,*7,*11",
                     "sv.add./ff=ns *3,*7,*11",
@@ -243,7 +243,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_15_predicates(self):
+    def test_15_predicates(self):
         expected = [
                     "sv.add./m=r3 *3,*7,*11",
                     "sv.add./m=1<<r3 *3,*7,*11",
@@ -260,14 +260,14 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_15_els(self):
+    def test_15_els(self):
         expected = [
                     "sv.stw/els *4,16(2)",
                     "sv.lfs/els *1,256(4)",
                         ]
         self._do_tst(expected)
 
-    def tst_16_bc(self):
+    def test_16_bc(self):
         """bigger list in test_pysvp64dis_branch.py, this one's "quick"
         """
         expected = [
@@ -287,20 +287,20 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_17_vli(self):
+    def test_17_vli(self):
         expected = [
                     "sv.add/ff=RC1/vli 3,7,11",
                     "sv.add/ff=~RC1/vli 3,7,11",
                         ]
         self._do_tst(expected)
 
-    def tst_18_sea(self):
+    def test_18_sea(self):
         expected = [
                     "sv.ldux/sea 5,6,7",
                         ]
         self._do_tst(expected)
 
-    def tst_19_ldst_idx_els(self):
+    def test_19_ldst_idx_els(self):
         expected = [
                     "sv.stdx/els *4,16,2",
                     "sv.stdx/els/sea *4,16,2",
@@ -309,7 +309,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_20_cmp(self):
+    def test_20_cmp(self):
         expected = [
                     "sv.cmp *4,1,*0,1",
                     "sv.cmp/ff=RC1 *4,1,*0,1",
@@ -321,7 +321,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_21_addex(self):
+    def test_21_addex(self):
         expected = [
                     "addex 5,3,2,0",
                     "sv.addex 5,3,2,0",
@@ -329,7 +329,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_22_ld(self):
+    def test_22_ld(self):
         expected = [
                     "ld 4,0(5)",
                     "ld 4,16(5)",       # sigh, needs magic-shift (D||0b00)
@@ -337,7 +337,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_23_lq(self):
+    def test_23_lq(self):
         expected = [
                     "lq 4,0(5)",
                     "lq 4,16(5)",      # ditto, magic-shift (DQ||0b0000)
@@ -346,14 +346,14 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_24_bc(self):
+    def test_24_bc(self):
         expected = [
                     "b 0x28",
                     "bc 16,0,-0xb4",
                         ]
         self._do_tst(expected)
 
-    def tst_25_stq(self):
+    def test_25_stq(self):
         expected = [
                     "stq 4,0(5)",
                     "stq 4,8(5)",
@@ -362,7 +362,7 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
-    def tst_26_sv_stq_vector_name(self):
+    def test_26_sv_stq_vector_name(self):
         expected = [
                     "sv.stq *4,16(*5)", # RSp not recognised as "vector" name
                         ]
@@ -370,11 +370,10 @@ class SVSTATETestCase(unittest.TestCase):
 
     def test_27_sc(self):
         expected = [
-                    #"sc 0",
-                    #"sc 1",
-                    #"scv 1",
-                    #"scv 2",
-                    "attn",
+                    "sc 0",
+                    "sc 1",
+                    "scv 1",
+                    "scv 2",
                         ]
         self._do_tst(expected)