From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 9 Mar 2015 11:48:45 +0000 (+0100)
Subject: liteeth: do not insert CRC/Preamble in simulation to allow direct connection to ether... 
X-Git-Tag: 24jan2021_ls180~2502
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5dbd8af4becbbcf498d2acc0851d39cb19bdb8d3;p=litex.git

liteeth: do not insert CRC/Preamble in simulation to allow direct connection to ethernet tap
---

diff --git a/misoclib/com/liteeth/mac/core/__init__.py b/misoclib/com/liteeth/mac/core/__init__.py
index 0eaa44a9..e30a8ced 100644
--- a/misoclib/com/liteeth/mac/core/__init__.py
+++ b/misoclib/com/liteeth/mac/core/__init__.py
@@ -1,6 +1,7 @@
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.generic import *
 from misoclib.com.liteeth.mac.core import gap, preamble, crc, padding, last_be
+from misoclib.com.liteeth.phy.sim import LiteEthPHYSim
 
 class LiteEthMACCore(Module, AutoCSR):
 	def __init__(self, phy, dw, endianness="big", with_hw_preamble_crc=True):
@@ -20,8 +21,11 @@ class LiteEthMACCore(Module, AutoCSR):
 		rx_pipeline += [rx_gap_checker]
 
 		# Preamble / CRC
-		if with_hw_preamble_crc:
+		if isinstance(phy, LiteEthPHYSim):
+			# In simulation, avoid CRC/Preamble to enable direct connection
+			# to the Ethernet tap.
 			self._hw_preamble_crc = CSRStatus(reset=1)
+		elif with_hw_preamble_crc:
 			# Preamble insert/check
 			preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw)
 			preamble_checker = preamble.LiteEthMACPreambleChecker(phy.dw)