From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 3 Nov 2020 13:40:28 +0000 (+0000)
Subject: change LVCMOS level on versa ecp5 jtag to 2.5v
X-Git-Tag: 24jan2021_ls180~118
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5dc6b70b0d12d431ef3aceff14a32ef1725c17c6;p=soc.git

change LVCMOS level on versa ecp5 jtag to 2.5v
---

diff --git a/src/soc/litex/florent/versa_ecp5.py b/src/soc/litex/florent/versa_ecp5.py
index 6bd917d8..75e33bc2 100755
--- a/src/soc/litex/florent/versa_ecp5.py
+++ b/src/soc/litex/florent/versa_ecp5.py
@@ -43,10 +43,10 @@ class VersaECP5TestSoC(versa_ecp5.BaseSoC):
         # define the pins, add as an extension, *then* request it
         jtag_ios = [
             ("jtag", 0,
-                Subsignal("tck", Pins("B19"), IOStandard("LVCMOS33")),
-                Subsignal("tms", Pins("B12"), IOStandard("LVCMOS33")),
-                Subsignal("tdi", Pins("B9"), IOStandard("LVCMOS33")),
-                Subsignal("tdo", Pins("E6"), IOStandard("LVCMOS33")),
+                Subsignal("tck", Pins("B19"), IOStandard("LVCMOS25")),
+                Subsignal("tms", Pins("B12"), IOStandard("LVCMOS25")),
+                Subsignal("tdi", Pins("B9"), IOStandard("LVCMOS25")),
+                Subsignal("tdo", Pins("E6"), IOStandard("LVCMOS25")),
             )
         ]
         self.platform.add_extension(jtag_ios)