From: lkcl <lkcl@web>
Date: Tue, 5 Apr 2022 00:29:27 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2882
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5de24f4276d720f1e3e0223515f74eb43ba8600a;p=libreriscv.git

---

diff --git a/HDL_workflow.mdwn b/HDL_workflow.mdwn
index d65d6411c..b5de78135 100644
--- a/HDL_workflow.mdwn
+++ b/HDL_workflow.mdwn
@@ -551,6 +551,15 @@ See [[HDL_workflow/nextpnr]] page for installation instructions of nextpnr with
 [[HDL_workflow/ECP5_FPGA]] for connecting up to JTAG with a ULX3S
 and the Lattice VERSA_ECP5.
 
+## Nextpnr-xilinx
+
+An open source place and route framework for Xilinx FPGAs using Project Xray. We will use it for Xilinx 7-series FPGAs like Artix-7.
+
+One of the ways to get Arty A7 100t Digilent FPGA board working.
+
+See [[HDL_workflow/nextpnr-xilinx]] for installation instructions and dependencies.
+
+
 ## Verilator
 
 The fastest Verilog and SystemVerilog simulator. It compiles Verilog to C++ or SystemC.
@@ -587,19 +596,11 @@ See [[HDL_workflow/cocotb]] page for installation instructions.
 
 A fully open source toolchain for the development of FPGAs. Currently it targets Xilinx 7-series, Lattice iCE40 and ECP5, Quicklogic EOS S3.
 
-Needed for the Arty A7 100t Digilent FPGA board.
+One way to get the Arty A7 100t Digilent FPGA board working.
 
 See [[HDL_workflow/symbiflow]] for installation instructions
 and dependencies.
 
-## Nextpnr-xilinx
-
-An open source place and route framework for Xilinx FPGAs using Project Xray. We will use it for Xilinx 7-series FPGAs like Artix-7.
-
-Needed for Arty A7 100t Digilent FPGA board.
-
-See [[HDL_workflow/nextpnr-xilinx]] for installation instructions and dependencies.
-
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 After going through the onboarding process and having agreed to take