From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 26 Sep 2018 08:03:08 +0000 (+0100)
Subject: check if register redirection is active, and if vectorisation enabled
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5de2a58256f8d26f27b551cf9664237949f40a31;p=riscv-isa-sim.git

check if register redirection is active, and if vectorisation enabled

check each register (if used) - this is what the #define USING_RD etc.
macros are for, to disable checks that are not needed
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index c340142..4199de0 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -15,6 +15,42 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
   int vlen = 1;
   sv_insn_t insn(bits, voffs);
   bool vectorop = false;
+  reg_t predicate = 0;
+  // identify which regs have had their CSR entries set as vectorised.
+  // really could do with a macro for-loop here... oh well...
+  // integer ops, RD, RS1, RS2, RS3 (use sv_int_tb)
+#ifdef USING_RD
+  vectorop &= check_reg(true, s_insn.rd());
+#endif
+#ifdef USING_RS1
+  vectorop &= check_reg(true, s_insn.rs1());
+#endif
+#ifdef USING_RS2
+  vectorop &= check_reg(true, s_insn.rs2());
+#endif
+#ifdef USING_RS2
+  vectorop &= check_reg(true, s_insn.rs3());
+#endif
+  // fp ops, RD, RS1, RS2, RS3 (use sv_fp_tb)
+#ifdef USING_FRD
+  vectorop &= check_reg(false, s_insn.frd());
+#endif
+#ifdef USING_FRS1
+  vectorop &= check_reg(false, s_insn.frs1());
+#endif
+#ifdef USING_FRS2
+  vectorop &= check_reg(false, s_insn.rs2());
+#endif
+#ifdef USING_FRS2
+  vectorop &= check_reg(false, s_insn.rs3());
+#endif
+
+  // if vectorop is set, one of the regs is not a scalar,
+  // so we must read the VL CSR and do a loop
+  if (vectorop)
+  {
+    // TODO: vlen = p->CSR(SIMPLEV_VL); // something like that...
+  }
   for (; voffs < vlen; voffs++)
   {
       #include INCLUDEFILE
diff --git a/riscv/sv.cc b/riscv/sv.cc
index 824541c..296e2d3 100644
--- a/riscv/sv.cc
+++ b/riscv/sv.cc
@@ -6,3 +6,24 @@ sv_reg_entry sv_fp_tb[NFPR];
 sv_pred_csr_entry sv_pred_csrs[SV_CSR_SZ];
 sv_pred_entry sv_pred_tb[NXPR];
 
+bool sv_check_reg(bool intreg, uint64_t reg)
+{
+  sv_reg_entry *r;
+  if (intreg)
+  {
+    r = &sv_int_tb[reg];
+  }
+  else
+  {
+    r = &sv_fp_tb[reg];
+  }
+  if (r->elwidth != 0)
+  {
+    // XXX raise exception
+  }
+  if (r->active && r->isvec)
+  {
+    return true;
+  }
+  return false;
+}
diff --git a/riscv/sv.h b/riscv/sv.h
index cd2f8fb..8c2bf3a 100644
--- a/riscv/sv.h
+++ b/riscv/sv.h
@@ -63,4 +63,6 @@ typedef struct {
 // 32 entries, only integer regs are predicates.
 extern sv_pred_entry sv_pred_tb[NXPR];
 
+bool sv_check_reg(bool intreg, uint64_t reg);
+
 #endif