From: Luke Kenneth Casson Leighton Date: Wed, 31 Jul 2019 11:29:44 +0000 (+0100) Subject: more cleanup X-Git-Tag: ls180-24jan2020~641 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5df38d971ee8bb6aad70b3f0b1fe45aa6e741dbc;p=ieee754fpu.git more cleanup --- diff --git a/src/ieee754/fpadd/add1.py b/src/ieee754/fpadd/add1.py index 70db8b47..15ca3c5e 100644 --- a/src/ieee754/fpadd/add1.py +++ b/src/ieee754/fpadd/add1.py @@ -1,17 +1,18 @@ -# IEEE Floating Point Adder (Single Precision) -# Copyright (C) Jonathan P Dawson 2013 -# 2013-12-12 +"""IEEE754 Floating Point Multiplier Pipeline + +Copyright (C) 2019 Luke Kenneth Casson Leighton + +""" from nmigen import Module, Signal, Elaboratable from nmigen.cli import main, verilog from math import log -from ieee754.fpcommon.fpbase import FPState from ieee754.fpcommon.postcalc import FPAddStage1Data -from .add0 import FPAddStage0Data +from ieee754.fpadd.add0 import FPAddStage0Data -class FPAddStage1Mod(FPState, Elaboratable): +class FPAddStage1Mod(Elaboratable): """ Second stage of add: preparation for normalisation. detects when tot sum is too big (tot[27] is kinda a carry bit) """ @@ -34,17 +35,17 @@ class FPAddStage1Mod(FPState, Elaboratable): """ links module to inputs and outputs """ m.submodules.add1 = self - #m.submodules.add1_out_overflow = self.o.of - m.d.comb += self.i.eq(i) def elaborate(self, platform): m = Module() - m.d.comb += self.o.z.eq(self.i.z) + comb = m.d.comb + + comb += self.o.z.eq(self.i.z) # tot[-1] (MSB) gets set when the sum overflows. shift result down with m.If(~self.i.out_do_z): with m.If(self.i.tot[-1]): - m.d.comb += [ + comb += [ self.o.z.m.eq(self.i.tot[4:]), self.o.of.m0.eq(self.i.tot[4]), self.o.of.guard.eq(self.i.tot[3]), @@ -54,7 +55,7 @@ class FPAddStage1Mod(FPState, Elaboratable): ] # tot[-1] (MSB) zero case with m.Else(): - m.d.comb += [ + comb += [ self.o.z.m.eq(self.i.tot[3:]), self.o.of.m0.eq(self.i.tot[3]), self.o.of.guard.eq(self.i.tot[2]), @@ -62,33 +63,8 @@ class FPAddStage1Mod(FPState, Elaboratable): self.o.of.sticky.eq(self.i.tot[0]) ] - m.d.comb += self.o.out_do_z.eq(self.i.out_do_z) - m.d.comb += self.o.oz.eq(self.i.oz) - m.d.comb += self.o.ctx.eq(self.i.ctx) + comb += self.o.out_do_z.eq(self.i.out_do_z) + comb += self.o.oz.eq(self.i.oz) + comb += self.o.ctx.eq(self.i.ctx) return m - - -class FPAddStage1(FPState): - - def __init__(self, pspec): - FPState.__init__(self, "add_1") - self.mod = FPAddStage1Mod(width) - self.out_z = FPNumBase(width, False) - self.out_of = Overflow() - self.norm_stb = Signal() - - def setup(self, m, i): - """ links module to inputs and outputs - """ - self.mod.setup(m, i) - - m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state - - m.d.sync += self.out_of.eq(self.mod.out_of) - m.d.sync += self.out_z.eq(self.mod.out_z) - m.d.sync += self.norm_stb.eq(1) - - def action(self, m): - m.next = "normalise_1" -