From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 11 Jun 2020 14:29:41 +0000 (+0100)
Subject: even more complexity in CompALUMulti, to deal with an edge case where
X-Git-Tag: div_pipeline~395
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e0126291abaf79314b5fc7d380ee9ed41cfdf82;p=soc.git

even more complexity in CompALUMulti, to deal with an edge case where
go-write is requested immediately (same cycle as go-req).
the set and reset on "req_l" happen to come in on the same cycle.
the result: the latch *remains* set high.
solution: record the go signals for one extra cycle (sync) and push
them into the req-reset and wr_any signals
---

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index a73d305b..2767a9c3 100644
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -194,6 +194,11 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         m.d.comb += alu_pulse.eq(alu_done & ~alu_done_dly)
         m.d.comb += alu_pulsem.eq(Repl(alu_pulse, self.n_dst))
 
+        # sigh bug where req_l gets both set and reset raised at same time
+        prev_wr_go = Signal(self.n_dst)
+        brd = Repl(self.busy_o, self.n_dst)
+        m.d.sync += prev_wr_go.eq(self.wr.go & brd)
+
         # write_requests all done
         # req_done works because any one of the last of the writes
         # is enough, when combined with when read-phase is done (rst_l.q)
@@ -201,7 +206,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         req_done = Signal(reset_less=True)
         m.d.comb += self.done_o.eq(self.busy_o & \
                                    ~((self.wr.rel & ~self.wrmask).bool()))
-        m.d.comb += wr_any.eq(self.wr.go.bool())
+        m.d.comb += wr_any.eq(self.wr.go.bool() | prev_wr_go.bool())
         m.d.comb += req_done.eq(wr_any & ~self.alu.n.ready_i & \
                 ((req_l.q & self.wrmask) == 0))
         # argh, complicated hack: if there are no regs to write,
@@ -238,8 +243,8 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         m.d.sync += src_l.r.eq(reset_r)
 
         # dest operand latch (not using issue_i)
-        m.d.comb += req_l.s.eq(alu_pulsem)
-        m.d.comb += req_l.r.eq(reset_w)
+        m.d.comb += req_l.s.eq(alu_pulsem & self.wrmask)
+        m.d.comb += req_l.r.eq(reset_w | prev_wr_go)
 
         # create a latch/register for the operand
         oper_r = self.opsubsetkls(name="oper_r")
diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index ee3c6fce..5128ca52 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -204,7 +204,6 @@ class TestRunner(FHDLTestCase):
                                 "respec %s" % \
                                 (bin(wr_rel_o), cu.rwid[1])
                     yield from set_cu_inputs(cu, inp)
-                    yield
                     rd_rel_o = yield cu.rd.rel
                     wr_rel_o = yield cu.wr.rel
                     wrmask = yield cu.wrmask