From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 7 May 2021 17:53:29 +0000 (+0100)
Subject: start setting DSISR bits but commented out
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e05bcf3da21f23d3814ba69b475d74075835293;p=soc.git

start setting DSISR bits but commented out
---

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index a2ad7a9a..ff13ec37 100644
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -132,10 +132,12 @@ class LoadStore1(PortInterfaceBase):
         with m.If(d_out.error):
             with m.If(d_out.cache_paradox):
                 comb += self.derror.eq(1)
-                #  dsisr(63 - 38) := not r2.req.load;
+                """
+                sync += self.dsisr[63 - 38].eq(~r2.req.load)
                 #    -- XXX there is no architected bit for this
                 #    -- (probably should be a machine check in fact)
-                #    dsisr(63 - 35) := d_in.cache_paradox;
+                sync += self.dsisr[63 - 35].eq(d_in.cache_paradox)
+                """
             with m.Else():
                 # Look up the translation for TLB miss
                 # and also for permission error and RC error