From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 25 Jun 2020 09:34:03 +0000 (+0100)
Subject: whitespace
X-Git-Tag: div_pipeline~279
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e089bb69791699803f52ccd5e2f2e502afc4f63;p=soc.git

whitespace
---

diff --git a/src/soc/experiment/lsmem.py b/src/soc/experiment/lsmem.py
index 7eec4035..29d1b4e8 100644
--- a/src/soc/experiment/lsmem.py
+++ b/src/soc/experiment/lsmem.py
@@ -53,6 +53,7 @@ def write_to_addr(dut, addr, value):
     while (yield dut.x_stall):
         yield
 
+
 def read_from_addr(dut, addr):
     yield dut.x_addr.eq(addr)
     yield dut.x_load.eq(1)
@@ -68,6 +69,7 @@ def read_from_addr(dut, addr):
     assert (yield dut.x_valid)
     return (yield dut.m_load_data)
 
+
 def write_byte(dut, addr, val):
     offset = addr & 0x3
     yield dut.x_addr.eq(addr)
@@ -81,6 +83,7 @@ def write_byte(dut, addr, val):
     while (yield dut.x_stall):
         yield
 
+
 def read_byte(dut, addr):
     offset = addr & 0x3
     yield dut.x_addr.eq(addr)
@@ -95,6 +98,7 @@ def read_byte(dut, addr):
     val = (yield dut.m_load_data)
     return (val >> (offset * 8)) & 0xff
 
+
 if __name__ == '__main__':
     m = Module()
     dut = TestMemLoadStoreUnit(regwid=32, addrwid=4)
diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py
index 4e6f1986..e04cc066 100644
--- a/src/soc/minerva/units/loadstore.py
+++ b/src/soc/minerva/units/loadstore.py
@@ -16,30 +16,30 @@ class LoadStoreUnitInterface:
         badwid = addr_wid-log2_int(mask_wid) # TODO: is this correct?
 
         # INPUTS
-        self.x_addr = Signal(addr_wid)       # The address used for loads/stores
+        self.x_addr = Signal(addr_wid)       # address used for loads/stores
         self.x_mask = Signal(mask_wid)       # Mask of which bytes to write
         self.x_load = Signal()               # set to do a memory load
         self.x_store = Signal()              # set to do a memory store
         self.x_store_data = Signal(data_wid) # The data to write when storing
         self.x_stall = Signal()              # do nothing until low
-        self.x_valid = Signal()              # Whether the x pipeline stage is
+        self.x_valid = Signal()              # Whether x pipeline stage is
                                              # currently enabled (I
                                              # think?). Set to 1 for #now
         self.m_stall = Signal()              # do nothing until low
-        self.m_valid = Signal()              # Whether the m pipeline stage is
+        self.m_valid = Signal()              # Whether m pipeline stage is
                                              # currently enabled. Set
                                              # to 1 for now
 
         # OUTPUTS
         self.x_busy = Signal()              # set when the memory is busy
         self.m_busy = Signal()              # set when the memory is busy
-        self.m_load_data = Signal(data_wid) # Data returned from a memory read
+        self.m_load_data = Signal(data_wid) # Data returned from memory read
         # Data validity is NOT indicated by m_valid or x_valid as
         # those are inputs. I believe it is valid on the next cycle
         # after raising m_load where busy is low
 
-        self.m_load_error = Signal()    # Whether there was an error when loading
-        self.m_store_error = Signal()   # Whether there was an error when storing
+        self.m_load_error = Signal()    # if there was an error when loading
+        self.m_store_error = Signal()   # if there was an error when storing
         self.m_badaddr = Signal(badwid) # The address of the load/store error