From: Richard Sandiford Date: Mon, 19 Aug 2013 19:54:41 +0000 (+0000) Subject: include/opcode/ X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e0dc5bae9dbbbcbd4156cafc941d3f984bfc792;p=binutils-gdb.git include/opcode/ * mips.h (M_DEXT, M_DINS): Delete. opcodes/ * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins" macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases. Use +H rather than +C for the real "dext". * mips-opc.c (mips_builtin_opcodes): Likewise. gas/ * config/tc-mips.c (report_bad_range, report_bad_field): Delete. (macro): Remove M_DEXT and M_DINS handling. gas/testsuite/ * gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS error messages to have the same form as the EXT and INS ones. * gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d, gas/mips/micromips-trap.d, gas/mips/micromips.d, gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect "dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu". --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 0a2f7b7e351..e5e34a69d48 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2013-08-19 Richard Sandiford + + * config/tc-mips.c (report_bad_range, report_bad_field): Delete. + (macro): Remove M_DEXT and M_DINS handling. + 2013-08-19 Richard Sandiford * config/tc-mips.c (mips_arg_info): Replace allow_nonconst and diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 4aa2493d0d0..f2c676878a1 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -4211,39 +4211,6 @@ mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) return FALSE; } -/* Report that user-supplied argument ARGNUM for INSN was VAL, but should - have been in the range [MIN_VAL, MAX_VAL]. PRINT_HEX says whether - this operand is normally printed in hex or decimal. */ - -static void -report_bad_range (struct mips_cl_insn *insn, int argnum, - offsetT val, int min_val, int max_val, - bfd_boolean print_hex) -{ - if (print_hex && val >= 0) - as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x]," - " was 0x%lx."), - argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val); - else if (print_hex) - as_bad (_("Operand %d of `%s' must be in the range [0x%x, 0x%x]," - " was %ld."), - argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val); - else - as_bad (_("Operand %d of `%s' must be in the range [%d, %d]," - " was %ld."), - argnum, insn->insn_mo->name, min_val, max_val, (unsigned long) val); -} - -/* Report an invalid combination of position and size operands for a bitfield - operation. POS and SIZE are the values that were given. */ - -static void -report_bad_field (offsetT pos, offsetT size) -{ - as_bad (_("Invalid field specification (position %ld, size %ld)"), - (unsigned long) pos, (unsigned long) size); -} - /* Information about an instruction argument that we're trying to match. */ struct mips_arg_info { @@ -9515,102 +9482,6 @@ macro (struct mips_cl_insn *ip, char *str) } break; - case M_DEXT: - { - /* Use unsigned arithmetic. */ - addressT pos; - addressT size; - - if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) - { - as_bad (_("Unsupported large constant")); - pos = size = 1; - } - else - { - pos = imm_expr.X_add_number; - size = imm2_expr.X_add_number; - } - - if (pos > 63) - { - report_bad_range (ip, 3, pos, 0, 63, FALSE); - pos = 1; - } - if (size == 0 || size > 64 || (pos + size - 1) > 63) - { - report_bad_field (pos, size); - size = 1; - } - - if (size <= 32 && pos < 32) - { - s = "dext"; - fmt = "t,r,+A,+C"; - } - else if (size <= 32) - { - s = "dextu"; - fmt = "t,r,+E,+H"; - } - else - { - s = "dextm"; - fmt = "t,r,+A,+G"; - } - macro_build ((expressionS *) NULL, s, fmt, op[0], op[1], (int) pos, - (int) (size - 1)); - } - break; - - case M_DINS: - { - /* Use unsigned arithmetic. */ - addressT pos; - addressT size; - - if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant) - { - as_bad (_("Unsupported large constant")); - pos = size = 1; - } - else - { - pos = imm_expr.X_add_number; - size = imm2_expr.X_add_number; - } - - if (pos > 63) - { - report_bad_range (ip, 3, pos, 0, 63, FALSE); - pos = 1; - } - if (size == 0 || size > 64 || (pos + size - 1) > 63) - { - report_bad_field (pos, size); - size = 1; - } - - if (pos < 32 && (pos + size - 1) < 32) - { - s = "dins"; - fmt = "t,r,+A,+B"; - } - else if (pos >= 32) - { - s = "dinsu"; - fmt = "t,r,+E,+F"; - } - else - { - s = "dinsm"; - fmt = "t,r,+A,+F"; - } - macro_build ((expressionS *) NULL, s, fmt, op[0], op[1], (int) pos, - (int) (pos + size - 1)); - } - break; - case M_DDIV_3: dbl = 1; case M_DIV_3: diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 03e804ad8ea..f9be128ef2d 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,12 @@ +2013-08-19 Richard Sandiford + + * gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS + error messages to have the same form as the EXT and INS ones. + * gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d, + gas/mips/micromips-trap.d, gas/mips/micromips.d, + gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect + "dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu". + 2013-08-19 Richard Sandiford * gas/mips/octeon-ill.l: Adjust expected output. diff --git a/gas/testsuite/gas/mips/ext-ill.l b/gas/testsuite/gas/mips/ext-ill.l index 606c047d9e4..55cbed83b59 100644 --- a/gas/testsuite/gas/mips/ext-ill.l +++ b/gas/testsuite/gas/mips/ext-ill.l @@ -1,6 +1,6 @@ .*: Assembler messages: .*:5: Error: operand 4 out of range `ext \$2,\$3,1,0' -.*:6: Error: Invalid field specification \(position 1, size 0\) +.*:6: Error: operand 4 out of range `dext \$2,\$3,1,0' .*:7: Error: operand 4 out of range `dextm \$2,\$3,31,2' .*:8: Error: operand 4 out of range `dextm \$2,\$3,1,32' .*:9: Error: operand 4 out of range `dextu \$2,\$3,33,0' diff --git a/gas/testsuite/gas/mips/micromips-insn32.d b/gas/testsuite/gas/mips/micromips-insn32.d index 5725043872d..d7092df5a30 100644 --- a/gas/testsuite/gas/mips/micromips-insn32.d +++ b/gas/testsuite/gas/mips/micromips-insn32.d @@ -6589,16 +6589,16 @@ Disassembly of section \.text: [ 0-9a-f]+: 0003 1d7c mflo v1 [ 0-9a-f]+: 5843 07ec dext v0,v1,0x1f,0x1 [ 0-9a-f]+: 5843 f82c dext v0,v1,0x0,0x20 -[ 0-9a-f]+: 5843 07e4 dextm v0,v1,0x1f,0x21 -[ 0-9a-f]+: 5843 07e4 dextm v0,v1,0x1f,0x21 -[ 0-9a-f]+: 5843 4854 dextu v0,v1,0x21,0xa -[ 0-9a-f]+: 5843 4854 dextu v0,v1,0x21,0xa +[ 0-9a-f]+: 5843 07e4 dext v0,v1,0x1f,0x21 +[ 0-9a-f]+: 5843 07e4 dext v0,v1,0x1f,0x21 +[ 0-9a-f]+: 5843 4854 dext v0,v1,0x21,0xa +[ 0-9a-f]+: 5843 4854 dext v0,v1,0x21,0xa [ 0-9a-f]+: 5843 ffcc dins v0,v1,0x1f,0x1 [ 0-9a-f]+: 5843 f80c dins v0,v1,0x0,0x20 -[ 0-9a-f]+: 5843 ffc4 dinsm v0,v1,0x1f,0x21 -[ 0-9a-f]+: 5843 ffc4 dinsm v0,v1,0x1f,0x21 -[ 0-9a-f]+: 5843 5074 dinsu v0,v1,0x21,0xa -[ 0-9a-f]+: 5843 5074 dinsu v0,v1,0x21,0xa +[ 0-9a-f]+: 5843 ffc4 dins v0,v1,0x1f,0x21 +[ 0-9a-f]+: 5843 ffc4 dins v0,v1,0x1f,0x21 +[ 0-9a-f]+: 5843 5074 dins v0,v1,0x21,0xa +[ 0-9a-f]+: 5843 5074 dins v0,v1,0x21,0xa [ 0-9a-f]+: 41a2 0000 lui v0,0x0 [ ]*[0-9a-f]+: R_MICROMIPS_HI16 test [ 0-9a-f]+: 3042 0000 addiu v0,v0,0 diff --git a/gas/testsuite/gas/mips/micromips-noinsn32.d b/gas/testsuite/gas/mips/micromips-noinsn32.d index 22bb62a3ddf..341a579bd06 100644 --- a/gas/testsuite/gas/mips/micromips-noinsn32.d +++ b/gas/testsuite/gas/mips/micromips-noinsn32.d @@ -6568,16 +6568,16 @@ Disassembly of section \.text: [ 0-9a-f]+: 4643 mflo v1 [ 0-9a-f]+: 5843 07ec dext v0,v1,0x1f,0x1 [ 0-9a-f]+: 5843 f82c dext v0,v1,0x0,0x20 -[ 0-9a-f]+: 5843 07e4 dextm v0,v1,0x1f,0x21 -[ 0-9a-f]+: 5843 07e4 dextm v0,v1,0x1f,0x21 -[ 0-9a-f]+: 5843 4854 dextu v0,v1,0x21,0xa -[ 0-9a-f]+: 5843 4854 dextu v0,v1,0x21,0xa +[ 0-9a-f]+: 5843 07e4 dext v0,v1,0x1f,0x21 +[ 0-9a-f]+: 5843 07e4 dext v0,v1,0x1f,0x21 +[ 0-9a-f]+: 5843 4854 dext v0,v1,0x21,0xa +[ 0-9a-f]+: 5843 4854 dext v0,v1,0x21,0xa [ 0-9a-f]+: 5843 ffcc dins v0,v1,0x1f,0x1 [ 0-9a-f]+: 5843 f80c dins v0,v1,0x0,0x20 -[ 0-9a-f]+: 5843 ffc4 dinsm v0,v1,0x1f,0x21 -[ 0-9a-f]+: 5843 ffc4 dinsm v0,v1,0x1f,0x21 -[ 0-9a-f]+: 5843 5074 dinsu v0,v1,0x21,0xa -[ 0-9a-f]+: 5843 5074 dinsu v0,v1,0x21,0xa +[ 0-9a-f]+: 5843 ffc4 dins v0,v1,0x1f,0x21 +[ 0-9a-f]+: 5843 ffc4 dins v0,v1,0x1f,0x21 +[ 0-9a-f]+: 5843 5074 dins v0,v1,0x21,0xa +[ 0-9a-f]+: 5843 5074 dins v0,v1,0x21,0xa [ 0-9a-f]+: 41a2 0000 lui v0,0x0 [ ]*[0-9a-f]+: R_MICROMIPS_HI16 test [ 0-9a-f]+: 3042 0000 addiu v0,v0,0 diff --git a/gas/testsuite/gas/mips/micromips-trap.d b/gas/testsuite/gas/mips/micromips-trap.d index 8c59ec5db57..16f82407b05 100644 --- a/gas/testsuite/gas/mips/micromips-trap.d +++ b/gas/testsuite/gas/mips/micromips-trap.d @@ -6559,16 +6559,16 @@ Disassembly of section \.text: [ 0-9a-f]+: 4643 mflo v1 [ 0-9a-f]+: 5843 07ec dext v0,v1,0x1f,0x1 [ 0-9a-f]+: 5843 f82c dext v0,v1,0x0,0x20 -[ 0-9a-f]+: 5843 07e4 dextm v0,v1,0x1f,0x21 -[ 0-9a-f]+: 5843 07e4 dextm v0,v1,0x1f,0x21 -[ 0-9a-f]+: 5843 4854 dextu v0,v1,0x21,0xa -[ 0-9a-f]+: 5843 4854 dextu v0,v1,0x21,0xa +[ 0-9a-f]+: 5843 07e4 dext v0,v1,0x1f,0x21 +[ 0-9a-f]+: 5843 07e4 dext v0,v1,0x1f,0x21 +[ 0-9a-f]+: 5843 4854 dext v0,v1,0x21,0xa +[ 0-9a-f]+: 5843 4854 dext v0,v1,0x21,0xa [ 0-9a-f]+: 5843 ffcc dins v0,v1,0x1f,0x1 [ 0-9a-f]+: 5843 f80c dins v0,v1,0x0,0x20 -[ 0-9a-f]+: 5843 ffc4 dinsm v0,v1,0x1f,0x21 -[ 0-9a-f]+: 5843 ffc4 dinsm v0,v1,0x1f,0x21 -[ 0-9a-f]+: 5843 5074 dinsu v0,v1,0x21,0xa -[ 0-9a-f]+: 5843 5074 dinsu v0,v1,0x21,0xa +[ 0-9a-f]+: 5843 ffc4 dins v0,v1,0x1f,0x21 +[ 0-9a-f]+: 5843 ffc4 dins v0,v1,0x1f,0x21 +[ 0-9a-f]+: 5843 5074 dins v0,v1,0x21,0xa +[ 0-9a-f]+: 5843 5074 dins v0,v1,0x21,0xa [ 0-9a-f]+: 41a2 0000 lui v0,0x0 [ ]*[0-9a-f]+: R_MICROMIPS_HI16 test [ 0-9a-f]+: 3042 0000 addiu v0,v0,0 diff --git a/gas/testsuite/gas/mips/micromips.d b/gas/testsuite/gas/mips/micromips.d index 6bd6bfa7aaf..9f54ec495ba 100644 --- a/gas/testsuite/gas/mips/micromips.d +++ b/gas/testsuite/gas/mips/micromips.d @@ -6646,16 +6646,16 @@ Disassembly of section \.text: [ 0-9a-f]+: 4643 mflo v1 [ 0-9a-f]+: 5843 07ec dext v0,v1,0x1f,0x1 [ 0-9a-f]+: 5843 f82c dext v0,v1,0x0,0x20 -[ 0-9a-f]+: 5843 07e4 dextm v0,v1,0x1f,0x21 -[ 0-9a-f]+: 5843 07e4 dextm v0,v1,0x1f,0x21 -[ 0-9a-f]+: 5843 4854 dextu v0,v1,0x21,0xa -[ 0-9a-f]+: 5843 4854 dextu v0,v1,0x21,0xa +[ 0-9a-f]+: 5843 07e4 dext v0,v1,0x1f,0x21 +[ 0-9a-f]+: 5843 07e4 dext v0,v1,0x1f,0x21 +[ 0-9a-f]+: 5843 4854 dext v0,v1,0x21,0xa +[ 0-9a-f]+: 5843 4854 dext v0,v1,0x21,0xa [ 0-9a-f]+: 5843 ffcc dins v0,v1,0x1f,0x1 [ 0-9a-f]+: 5843 f80c dins v0,v1,0x0,0x20 -[ 0-9a-f]+: 5843 ffc4 dinsm v0,v1,0x1f,0x21 -[ 0-9a-f]+: 5843 ffc4 dinsm v0,v1,0x1f,0x21 -[ 0-9a-f]+: 5843 5074 dinsu v0,v1,0x21,0xa -[ 0-9a-f]+: 5843 5074 dinsu v0,v1,0x21,0xa +[ 0-9a-f]+: 5843 ffc4 dins v0,v1,0x1f,0x21 +[ 0-9a-f]+: 5843 ffc4 dins v0,v1,0x1f,0x21 +[ 0-9a-f]+: 5843 5074 dins v0,v1,0x21,0xa +[ 0-9a-f]+: 5843 5074 dins v0,v1,0x21,0xa [ 0-9a-f]+: 41a2 0000 lui v0,0x0 [ ]*[0-9a-f]+: R_MICROMIPS_HI16 test [ 0-9a-f]+: 3042 0000 addiu v0,v0,0 diff --git a/gas/testsuite/gas/mips/micromips@mips64r2.d b/gas/testsuite/gas/mips/micromips@mips64r2.d index 3bc759d623a..f428bcf41a7 100644 --- a/gas/testsuite/gas/mips/micromips@mips64r2.d +++ b/gas/testsuite/gas/mips/micromips@mips64r2.d @@ -9,28 +9,28 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> 5843 002c dext \$2,\$3,0x0,0x1 [0-9a-f]+ <[^>]*> 5843 f82c dext \$2,\$3,0x0,0x20 -[0-9a-f]+ <[^>]*> 5843 0024 dextm \$2,\$3,0x0,0x21 -[0-9a-f]+ <[^>]*> 5843 f824 dextm \$2,\$3,0x0,0x40 +[0-9a-f]+ <[^>]*> 5843 0024 dext \$2,\$3,0x0,0x21 +[0-9a-f]+ <[^>]*> 5843 f824 dext \$2,\$3,0x0,0x40 [0-9a-f]+ <[^>]*> 5843 07ec dext \$2,\$3,0x1f,0x1 [0-9a-f]+ <[^>]*> 5843 ffec dext \$2,\$3,0x1f,0x20 -[0-9a-f]+ <[^>]*> 5843 07e4 dextm \$2,\$3,0x1f,0x21 -[0-9a-f]+ <[^>]*> 5843 0014 dextu \$2,\$3,0x20,0x1 -[0-9a-f]+ <[^>]*> 5843 f814 dextu \$2,\$3,0x20,0x20 -[0-9a-f]+ <[^>]*> 5843 07d4 dextu \$2,\$3,0x3f,0x1 -[0-9a-f]+ <[^>]*> 5843 5aa4 dextm \$2,\$3,0xa,0x2c -[0-9a-f]+ <[^>]*> 5843 5a94 dextu \$2,\$3,0x2a,0xc +[0-9a-f]+ <[^>]*> 5843 07e4 dext \$2,\$3,0x1f,0x21 +[0-9a-f]+ <[^>]*> 5843 0014 dext \$2,\$3,0x20,0x1 +[0-9a-f]+ <[^>]*> 5843 f814 dext \$2,\$3,0x20,0x20 +[0-9a-f]+ <[^>]*> 5843 07d4 dext \$2,\$3,0x3f,0x1 +[0-9a-f]+ <[^>]*> 5843 5aa4 dext \$2,\$3,0xa,0x2c +[0-9a-f]+ <[^>]*> 5843 5a94 dext \$2,\$3,0x2a,0xc [0-9a-f]+ <[^>]*> 5843 000c dins \$2,\$3,0x0,0x1 [0-9a-f]+ <[^>]*> 5843 f80c dins \$2,\$3,0x0,0x20 -[0-9a-f]+ <[^>]*> 5843 0004 dinsm \$2,\$3,0x0,0x21 -[0-9a-f]+ <[^>]*> 5843 f804 dinsm \$2,\$3,0x0,0x40 +[0-9a-f]+ <[^>]*> 5843 0004 dins \$2,\$3,0x0,0x21 +[0-9a-f]+ <[^>]*> 5843 f804 dins \$2,\$3,0x0,0x40 [0-9a-f]+ <[^>]*> 5843 ffcc dins \$2,\$3,0x1f,0x1 -[0-9a-f]+ <[^>]*> 5843 07c4 dinsm \$2,\$3,0x1f,0x2 -[0-9a-f]+ <[^>]*> 5843 ffc4 dinsm \$2,\$3,0x1f,0x21 -[0-9a-f]+ <[^>]*> 5843 0034 dinsu \$2,\$3,0x20,0x1 -[0-9a-f]+ <[^>]*> 5843 f834 dinsu \$2,\$3,0x20,0x20 -[0-9a-f]+ <[^>]*> 5843 fff4 dinsu \$2,\$3,0x3f,0x1 -[0-9a-f]+ <[^>]*> 5843 aa84 dinsm \$2,\$3,0xa,0x2c -[0-9a-f]+ <[^>]*> 5843 aab4 dinsu \$2,\$3,0x2a,0xc +[0-9a-f]+ <[^>]*> 5843 07c4 dins \$2,\$3,0x1f,0x2 +[0-9a-f]+ <[^>]*> 5843 ffc4 dins \$2,\$3,0x1f,0x21 +[0-9a-f]+ <[^>]*> 5843 0034 dins \$2,\$3,0x20,0x1 +[0-9a-f]+ <[^>]*> 5843 f834 dins \$2,\$3,0x20,0x20 +[0-9a-f]+ <[^>]*> 5843 fff4 dins \$2,\$3,0x3f,0x1 +[0-9a-f]+ <[^>]*> 5843 aa84 dins \$2,\$3,0xa,0x2c +[0-9a-f]+ <[^>]*> 5843 aab4 dins \$2,\$3,0x2a,0xc [0-9a-f]+ <[^>]*> 5b2a e0c8 dror32 \$25,\$10,0x1c [0-9a-f]+ <[^>]*> 5b2a 20c0 dror \$25,\$10,0x4 [0-9a-f]+ <[^>]*> 5b2a e0c0 dror \$25,\$10,0x1c diff --git a/gas/testsuite/gas/mips/mips64r2-ill.l b/gas/testsuite/gas/mips/mips64r2-ill.l index aa32a444617..74da418a766 100644 --- a/gas/testsuite/gas/mips/mips64r2-ill.l +++ b/gas/testsuite/gas/mips/mips64r2-ill.l @@ -1,12 +1,12 @@ .*: Assembler messages: -.*:12: Error: Operand 3 of `dext' must be in the range \[0, 63\], was -1. -.*:15: Error: Operand 3 of `dext' must be in the range \[0, 63\], was 64. -.*:18: Error: Invalid field specification \(position 0, size 0\) -.*:21: Error: Invalid field specification \(position 0, size 65\) -.*:31: Error: Invalid field specification \(position 1, size 64\) -.*:33: Error: Invalid field specification \(position 63, size 2\) -.*:34: Error: Invalid field specification \(position 63, size 63\) -.*:35: Error: Invalid field specification \(position 63, size 64\) +.*:12: Error: operand 3 out of range `dext \$4,\$5,-1,1' +.*:15: Error: operand 3 out of range `dext \$4,\$5,64,1' +.*:18: Error: operand 4 out of range `dext \$4,\$5,0,0' +.*:21: Error: operand 4 out of range `dext \$4,\$5,0,65' +.*:31: Error: operand 4 out of range `dext \$4,\$5,1,64' +.*:33: Error: operand 4 out of range `dext \$4,\$5,63,2' +.*:34: Error: operand 4 out of range `dext \$4,\$5,63,63' +.*:35: Error: operand 4 out of range `dext \$4,\$5,63,64' .*:40: Error: operand 3 out of range `dextm \$4,\$5,-1,33' .*:43: Error: operand 3 out of range `dextm \$4,\$5,32,33' .*:46: Error: operand 4 out of range `dextm \$4,\$5,0,32' @@ -23,14 +23,14 @@ .*:89: Error: operand 4 out of range `dextu \$4,\$5,63,2' .*:90: Error: operand 4 out of range `dextu \$4,\$5,63,31' .*:91: Error: operand 4 out of range `dextu \$4,\$5,63,32' -.*:96: Error: Operand 3 of `dins' must be in the range \[0, 63\], was -1. -.*:99: Error: Operand 3 of `dins' must be in the range \[0, 63\], was 64. -.*:102: Error: Invalid field specification \(position 0, size 0\) -.*:105: Error: Invalid field specification \(position 0, size 65\) -.*:115: Error: Invalid field specification \(position 1, size 64\) -.*:117: Error: Invalid field specification \(position 63, size 2\) -.*:118: Error: Invalid field specification \(position 63, size 63\) -.*:119: Error: Invalid field specification \(position 63, size 64\) +.*:96: Error: operand 3 out of range `dins \$4,\$5,-1,1' +.*:99: Error: operand 3 out of range `dins \$4,\$5,64,1' +.*:102: Error: operand 4 out of range `dins \$4,\$5,0,0' +.*:105: Error: operand 4 out of range `dins \$4,\$5,0,65' +.*:115: Error: operand 4 out of range `dins \$4,\$5,1,64' +.*:117: Error: operand 4 out of range `dins \$4,\$5,63,2' +.*:118: Error: operand 4 out of range `dins \$4,\$5,63,63' +.*:119: Error: operand 4 out of range `dins \$4,\$5,63,64' .*:124: Error: operand 3 out of range `dinsm \$4,\$5,-1,33' .*:127: Error: operand 3 out of range `dinsm \$4,\$5,32,33' .*:130: Error: operand 4 out of range `dinsm \$4,\$5,31,1' diff --git a/gas/testsuite/gas/mips/mips64r2.d b/gas/testsuite/gas/mips/mips64r2.d index 8d336112334..72431827288 100644 --- a/gas/testsuite/gas/mips/mips64r2.d +++ b/gas/testsuite/gas/mips/mips64r2.d @@ -8,28 +8,28 @@ Disassembly of section .text: 0+0000 <[^>]*> 7c620003 dext \$2,\$3,0x0,0x1 0+0004 <[^>]*> 7c62f803 dext \$2,\$3,0x0,0x20 -0+0008 <[^>]*> 7c620001 dextm \$2,\$3,0x0,0x21 -0+000c <[^>]*> 7c62f801 dextm \$2,\$3,0x0,0x40 +0+0008 <[^>]*> 7c620001 dext \$2,\$3,0x0,0x21 +0+000c <[^>]*> 7c62f801 dext \$2,\$3,0x0,0x40 0+0010 <[^>]*> 7c6207c3 dext \$2,\$3,0x1f,0x1 0+0014 <[^>]*> 7c62ffc3 dext \$2,\$3,0x1f,0x20 -0+0018 <[^>]*> 7c6207c1 dextm \$2,\$3,0x1f,0x21 -0+001c <[^>]*> 7c620002 dextu \$2,\$3,0x20,0x1 -0+0020 <[^>]*> 7c62f802 dextu \$2,\$3,0x20,0x20 -0+0024 <[^>]*> 7c6207c2 dextu \$2,\$3,0x3f,0x1 -0+0028 <[^>]*> 7c625a81 dextm \$2,\$3,0xa,0x2c -0+002c <[^>]*> 7c625a82 dextu \$2,\$3,0x2a,0xc +0+0018 <[^>]*> 7c6207c1 dext \$2,\$3,0x1f,0x21 +0+001c <[^>]*> 7c620002 dext \$2,\$3,0x20,0x1 +0+0020 <[^>]*> 7c62f802 dext \$2,\$3,0x20,0x20 +0+0024 <[^>]*> 7c6207c2 dext \$2,\$3,0x3f,0x1 +0+0028 <[^>]*> 7c625a81 dext \$2,\$3,0xa,0x2c +0+002c <[^>]*> 7c625a82 dext \$2,\$3,0x2a,0xc 0+0030 <[^>]*> 7c620007 dins \$2,\$3,0x0,0x1 0+0034 <[^>]*> 7c62f807 dins \$2,\$3,0x0,0x20 -0+0038 <[^>]*> 7c620005 dinsm \$2,\$3,0x0,0x21 -0+003c <[^>]*> 7c62f805 dinsm \$2,\$3,0x0,0x40 +0+0038 <[^>]*> 7c620005 dins \$2,\$3,0x0,0x21 +0+003c <[^>]*> 7c62f805 dins \$2,\$3,0x0,0x40 0+0040 <[^>]*> 7c62ffc7 dins \$2,\$3,0x1f,0x1 -0+0044 <[^>]*> 7c6207c5 dinsm \$2,\$3,0x1f,0x2 -0+0048 <[^>]*> 7c62ffc5 dinsm \$2,\$3,0x1f,0x21 -0+004c <[^>]*> 7c620006 dinsu \$2,\$3,0x20,0x1 -0+0050 <[^>]*> 7c62f806 dinsu \$2,\$3,0x20,0x20 -0+0054 <[^>]*> 7c62ffc6 dinsu \$2,\$3,0x3f,0x1 -0+0058 <[^>]*> 7c62aa85 dinsm \$2,\$3,0xa,0x2c -0+005c <[^>]*> 7c62aa86 dinsu \$2,\$3,0x2a,0xc +0+0044 <[^>]*> 7c6207c5 dins \$2,\$3,0x1f,0x2 +0+0048 <[^>]*> 7c62ffc5 dins \$2,\$3,0x1f,0x21 +0+004c <[^>]*> 7c620006 dins \$2,\$3,0x20,0x1 +0+0050 <[^>]*> 7c62f806 dins \$2,\$3,0x20,0x20 +0+0054 <[^>]*> 7c62ffc6 dins \$2,\$3,0x3f,0x1 +0+0058 <[^>]*> 7c62aa85 dins \$2,\$3,0xa,0x2c +0+005c <[^>]*> 7c62aa86 dins \$2,\$3,0x2a,0xc 0+0060 <[^>]*> 002acf3e dror32 \$25,\$10,0x1c 0+0064 <[^>]*> 002ac93a dror \$25,\$10,0x4 0+0068 <[^>]*> 002acf3a dror \$25,\$10,0x1c diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 19fd1b39850..bacadb0eaaa 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2013-08-19 Richard Sandiford + + * mips.h (M_DEXT, M_DINS): Delete. + 2013-08-19 Richard Sandiford * mips.h (OP_OPTIONAL_REG): New mips_operand_type. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 6860fa7945b..c768cf255f5 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1354,8 +1354,6 @@ enum M_DDIV_3I, M_DDIVU_3, M_DDIVU_3I, - M_DEXT, - M_DINS, M_DIV_3, M_DIV_3I, M_DIVU_3, diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index b4840ee5301..af6ba2be956 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2013-08-19 Richard Sandiford + + * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins" + macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases. + Use +H rather than +C for the real "dext". + * mips-opc.c (mips_builtin_opcodes): Likewise. + 2013-08-19 Richard Sandiford * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros. diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index 33dd57e545e..da1f708d97e 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -544,8 +544,9 @@ const struct mips_opcode micromips_opcodes[] = {"dclo", "t,s", 0x58004b3c, 0xfc00ffff, WR_1|RD_2, 0, I3, 0, 0 }, {"dclz", "t,s", 0x58005b3c, 0xfc00ffff, WR_1|RD_2, 0, I3, 0, 0 }, {"deret", "", 0x0000e37c, 0xffffffff, NODS, 0, I1, 0, 0 }, -{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I3, 0, 0 }, -{"dext", "t,r,+A,+C", 0x5800002c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, +{"dext", "t,r,+A,+H", 0x5800002c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, +{"dext", "t,r,+A,+G", 0x58000024, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dextm */ +{"dext", "t,r,+E,+H", 0x58000014, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dextu */ {"dextm", "t,r,+A,+G", 0x58000024, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, {"dextu", "t,r,+E,+H", 0x58000014, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* For ddiv, see the comments about div. */ @@ -560,8 +561,9 @@ const struct mips_opcode micromips_opcodes[] = {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3, 0, 0 }, {"di", "", 0x0000477c, 0xffffffff, RD_C0, 0, I1, 0, 0 }, {"di", "s", 0x0000477c, 0xffe0ffff, WR_1|RD_C0, 0, I1, 0, 0 }, -{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I3, 0, 0 }, {"dins", "t,r,+A,+B", 0x5800000c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, +{"dins", "t,r,+A,+F", 0x58000004, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dinsm */ +{"dins", "t,r,+E,+F", 0x58000034, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dinsu */ {"dinsm", "t,r,+A,+F", 0x58000004, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, {"dinsu", "t,r,+E,+F", 0x58000034, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* The MIPS assembler treats the div opcode with two operands as diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 7fdc93865a9..6bdf60cd4d7 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -921,8 +921,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, {"deret", "", 0x4200001f, 0xffffffff, NODS, 0, I32|G2, 0, 0 }, -{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65, 0, 0 }, -{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, +{"dext", "t,r,+A,+H", 0x7c000003, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, +{"dext", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dextm */ +{"dext", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dextu */ {"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, {"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* For ddiv, see the comments about div. */ @@ -936,8 +937,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {"di", "", 0x42000039, 0xffffffff, WR_C0, 0, EE, 0, 0 }, {"di", "", 0x41606000, 0xffffffff, WR_C0, 0, I33, 0, 0 }, {"di", "t", 0x41606000, 0xffe0ffff, WR_1|WR_C0, 0, I33, 0, 0 }, -{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65, 0, 0 }, {"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, +{"dins", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dinsm */ +{"dins", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dinsu */ {"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, {"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* The MIPS assembler treats the div opcode with two operands as