From: lkcl Date: Sun, 3 Jul 2022 11:55:43 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~1390 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e1ac44af9d92f2f904914dad46d2c32d802ea5d;p=libreriscv.git --- diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn index a7f5f2dd9..c3c2100ca 100644 --- a/openpower/sv.mdwn +++ b/openpower/sv.mdwn @@ -120,7 +120,11 @@ Core SVP64 instructions: * [[sv/setvl]] the Cray-style "Vector Length" instruction * [[sv/remap]] "Remapping" for Matrix Multiply and RGB "Structure Packing" -* [[sv/svstep]] Key stepping instruction for Vertical-First Mode + as well as Indexing. Describes svindex, svremap and svshape and + associated SPRs. +* [[sv/svstep]] Key stepping instruction, primarily for + Vertical-First Mode and also providing traditional "Vector Iota" + capability. *Please note: there are only five instructions in the whole of SV. Beyond this point are additional **Scalar** instructions related to @@ -140,7 +144,8 @@ Some of these Scalar instructions are specifically designed to make Scalable Vector binaries more efficient, such as the crweird group. Others are to bring the Scalar Power ISA up-to-date within specific workloads, -such as a Javascript Rounding instruction. None of them are strictly +such as a Javascript Rounding instruction +(which saves 35 instructions includibg 5 branches). None of them are strictly necessary but performance and power consumption may be (or, is already) compromised in certain workloads and use-cases without them.