From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 16:37:18 +0000 (-0800)
Subject: Handle reset logic in latches
X-Git-Tag: yosys-0.9~232^2~27
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e24251a61b8798e597ac49bdc8aff2f378f625d;p=yosys.git

Handle reset logic in latches
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 0414d3db3..c3cc6b321 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -134,8 +134,23 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
         RTLIL::Wire *d_wire = createWireIfNotExists(l2);
 
         module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
-        // AIGER latches are assumed to be initialized to zero
-        q_wire->attributes["\\init"] = RTLIL::Const(0);
+
+        if (f.peek() == ' ') {
+            if (!(f >> l3))
+                log_error("Line %d cannot be interpreted as a latch!\n", line_count);
+
+            if (l3 == 0 || l3 == 1)
+                q_wire->attributes["\\init"] = RTLIL::Const(0);
+            else if (l3 == l1) {
+                //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx);
+            }
+            else
+                log_error("Line %d has invalid reset literal for latch!\n", line_count);
+        }
+        else {
+            // AIGER latches are assumed to be initialized to zero
+            q_wire->attributes["\\init"] = RTLIL::Const(0);
+        }
         latches.push_back(q_wire);
     }