From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Mar 2020 21:57:10 +0000 (-0700)
Subject: opt_expr: add $alu tests
X-Git-Tag: working-ls180~709^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e2562f1a2e4cfa53c80f9ca6200aecc4cc6fd9b;p=yosys.git

opt_expr: add $alu tests
---

diff --git a/tests/opt/opt_expr_alu.ys b/tests/opt/opt_expr_alu.ys
new file mode 100644
index 000000000..a3361ca43
--- /dev/null
+++ b/tests/opt/opt_expr_alu.ys
@@ -0,0 +1,63 @@
+read_verilog <<EOT
+module test(input a, output [1:0] y);
+assign y = {a,1'b0} + 1'b1;
+endmodule
+EOT
+
+alumacc
+equiv_opt opt_expr -fine
+design -load postopt
+select -assert-count 1 t:$pos
+select -assert-count none t:$pos t:* %D
+
+
+design -reset
+read_verilog <<EOT
+module test(input a, output [1:0] y);
+assign y = {a,1'b1} + 1'b1;
+endmodule
+EOT
+
+alumacc
+select -assert-count 1 t:$alu
+select -assert-count none t:$alu t:* %D
+
+
+design -reset
+read_verilog <<EOT
+module test(input a, output [1:0] y);
+assign y = {a,1'b1} - 1'b1;
+endmodule
+EOT
+
+equiv_opt opt_expr -fine
+design -load postopt
+select -assert-count 1 t:$pos
+select -assert-count none t:$pos t:* %D
+
+
+design -reset
+read_verilog <<EOT
+module test(input a, output [3:0] y);
+assign y = {a,3'b101} - 1'b1;
+endmodule
+EOT
+
+equiv_opt opt_expr -fine
+design -load postopt
+select -assert-count 1 t:$pos
+select -assert-count none t:$pos t:* %D
+
+
+design -reset
+read_verilog <<EOT
+module test(input a, output [3:0] y);
+assign y = {a,3'b101} - 1'b1;
+endmodule
+EOT
+
+alumacc
+equiv_opt opt_expr -fine
+design -load postopt
+select -assert-count 1 t:$pos
+select -assert-count none t:$pos t:* %D