From: Kevin Buettner <kevinb@redhat.com>
Date: Wed, 16 Feb 2000 04:11:25 +0000 (+0000)
Subject: Fix wording regarding Intel's IA-64 architecture.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e35df8e620de35759c79da38c1a3c686072d1e5;p=binutils-gdb.git

Fix wording regarding Intel's IA-64 architecture.
---

diff --git a/gdb/doc/ChangeLog b/gdb/doc/ChangeLog
index e2422d58255..e5b6e707036 100644
--- a/gdb/doc/ChangeLog
+++ b/gdb/doc/ChangeLog
@@ -1,3 +1,8 @@
+2000-02-15  Kevin Buettner  <kevinb@redhat.com>
+
+	* agentexpr.texi: Fix wording regarding Intel's IA-64
+	architecture.
+
 2000-01-16  Tom Tromey  <tromey@cygnus.com>
 
 	* gdb.texinfo (Breakpoints): Mention breakpoint ranges.
diff --git a/gdb/doc/agentexpr.texi b/gdb/doc/agentexpr.texi
index 4b790f56af2..54186675e28 100644
--- a/gdb/doc/agentexpr.texi
+++ b/gdb/doc/agentexpr.texi
@@ -798,7 +798,7 @@ When we add side-effects, we should add this.
 
 @item Why does the @code{reg} bytecode take a 16-bit register number?
 
-Intel's IA64-architecture, Merced, has 128 general-purpose registers,
+Intel's IA-64 architecture has 128 general-purpose registers,
 and 128 floating-point registers, and I'm sure it has some random
 control registers.