From: lkcl Date: Sun, 21 Aug 2022 12:52:25 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~813 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e36d82c6fe4da66b79efec5664d6a3abba033f6;p=libreriscv.git --- diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index 43d7249df..cdf3b53f9 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -635,8 +635,15 @@ These are not insurmountable problems: there do exist workarounds. For example it is possible to set up Matrix REMAP to perform the same job as Pack/Unpack, at which point the LD/ST "Saturation" mode may be used, saving on costly intermediary registers at double the LD -width. Also, although potentially costly it may be possible to -use Indexed Mode after using `svstep` to compute a sequence of +width if a Saturated MV had to be involved. + +Also, the LD/ST Indexed Mode can be element-strided (RB as +a Scalar, times +the element index), or, if that is not enough, +although potentially costly it may be possible to +use `svstep` to compute a Vector RB sequence of Indices, then activate either `sz` or `dz` as required, as a workaround for LDST Immediate only having `zz`. +Simple-V is powerful but it cannot do everything! There is just not +enough space and so some compromises had to be made.