From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 15 Feb 2014 14:42:10 +0000 (+0100)
Subject: Correctly convert constants to RTLIL (fixed undef handling)
X-Git-Tag: yosys-0.2.0~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e39e6ece28e1145a04e8f00f9ac4f5d9a738acf;p=yosys.git

Correctly convert constants to RTLIL (fixed undef handling)
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index d92da4000..12fe23fd8 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -905,18 +905,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			if (width_hint < 0)
 				detectSignWidth(width_hint, sign_hint);
 
-			RTLIL::SigChunk chunk;
-			chunk.wire = NULL;
-			chunk.data.bits = bits;
-			chunk.width = bits.size();
-			chunk.offset = 0;
-
-			RTLIL::SigSpec sig;
-			sig.chunks.push_back(chunk);
-			sig.width = chunk.width;
-
 			is_signed = sign_hint;
-			return sig;
+			return RTLIL::SigSpec(bitsAsConst(width_hint, sign_hint));
 		}
 
 	// simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node