From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 29 Mar 2019 11:43:19 +0000 (+0000)
Subject: move FPID to fpbase
X-Git-Tag: ls180-24jan2020~1402
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e46ed71a70da6ca56b9afbe91789389212ca9b5;p=ieee754fpu.git

move FPID to fpbase
---

diff --git a/src/add/fpbase.py b/src/add/fpbase.py
index 3886332a..30c3a5c4 100644
--- a/src/add/fpbase.py
+++ b/src/add/fpbase.py
@@ -614,4 +614,18 @@ class FPState(FPBase):
             setattr(self, k, v)
 
 
+class FPID:
+    def __init__(self, id_wid):
+        self.id_wid = id_wid
+        if self.id_wid:
+            self.in_mid = Signal(id_wid, reset_less=True)
+            self.out_mid = Signal(id_wid, reset_less=True)
+        else:
+            self.in_mid = None
+            self.out_mid = None
+
+    def idsync(self, m):
+        if self.id_wid is not None:
+            m.d.sync += self.out_mid.eq(self.in_mid)
+
 
diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 112e7cf2..a86828db 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -14,7 +14,7 @@ from singlepipe import (ControlBase, StageChain, UnbufferedPipeline,
 from multipipe import CombMuxOutPipe
 from multipipe import PriorityCombMuxInPipe
 
-from fpbase import FPState
+from fpbase import FPState, FPID
 from fpcommon.getop import (FPGetOpMod, FPGetOp, FPNumBase2Ops, FPADDBaseData,                              FPGet2OpMod, FPGet2Op)
 from fpcommon.denorm import (FPSCData, FPAddDeNormMod, FPAddDeNorm)
 from fpcommon.postcalc import FPAddStage1Data
@@ -142,21 +142,6 @@ class FPAddSpecialCasesMod:
         return m
 
 
-class FPID:
-    def __init__(self, id_wid):
-        self.id_wid = id_wid
-        if self.id_wid:
-            self.in_mid = Signal(id_wid, reset_less=True)
-            self.out_mid = Signal(id_wid, reset_less=True)
-        else:
-            self.in_mid = None
-            self.out_mid = None
-
-    def idsync(self, m):
-        if self.id_wid is not None:
-            m.d.sync += self.out_mid.eq(self.in_mid)
-
-
 class FPAddSpecialCases(FPState):
     """ special cases: NaNs, infs, zeros, denormalised
         NOTE: some of these are unique to add.  see "Special Operations"