From: Wilco Dijkstra <wdijkstr@arm.com>
Date: Thu, 26 May 2016 12:12:20 +0000 (+0000)
Subject: SIMD operations like combine prefer to have their operands in FP registers,
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e4d7abeeea05faaa19d97c4693d5ae6c660a831;p=gcc.git

SIMD operations like combine prefer to have their operands in FP registers,

so increase the cost of integer registers slightly to avoid unnecessary int<->FP
moves. This improves register allocation of scalar SIMD operations.

        * config/aarch64/aarch64-simd.md (aarch64_combinez):
        Add ? to integer variant.
        (aarch64_combinez_be): Likewise.

From-SVN: r236770
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b1cd89ec209..b52e581d60a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2016-05-26  Wilco Dijkstra  <wdijkstr@arm.com>
+
+	* config/aarch64/aarch64-simd.md (aarch64_combinez):
+	Add ? to integer variant.
+	(aarch64_combinez_be): Likewise.
+
 2016-05-26  Jakub Jelinek  <jakub@redhat.com>
 
 	* config/i386/sse.md (*vcvtps2ph_store<mask_name>): Use v constraint
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 59a578f5937..3318c2155f5 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -2622,7 +2622,7 @@
 (define_insn "*aarch64_combinez<mode>"
   [(set (match_operand:<VDBL> 0 "register_operand" "=w,w,w")
         (vec_concat:<VDBL>
-	   (match_operand:VD_BHSI 1 "general_operand" "w,r,m")
+	   (match_operand:VD_BHSI 1 "general_operand" "w,?r,m")
 	   (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz,Dz,Dz")))]
   "TARGET_SIMD && !BYTES_BIG_ENDIAN"
   "@
@@ -2638,7 +2638,7 @@
   [(set (match_operand:<VDBL> 0 "register_operand" "=w,w,w")
         (vec_concat:<VDBL>
 	   (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz,Dz,Dz")
-	   (match_operand:VD_BHSI 1 "general_operand" "w,r,m")))]
+	   (match_operand:VD_BHSI 1 "general_operand" "w,?r,m")))]
   "TARGET_SIMD && BYTES_BIG_ENDIAN"
   "@
    mov\\t%0.8b, %1.8b