From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 1 May 2015 18:33:56 +0000 (+0200)
Subject: litescope: add basic LiteScopeUSB2WishboneFTDIDriver (working but need to be optimized)
X-Git-Tag: 24jan2021_ls180~2275
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e649a657771371f68837004e89640f40471862f;p=litex.git

litescope: add basic LiteScopeUSB2WishboneFTDIDriver (working but need to be optimized)
---

diff --git a/misoclib/com/liteusb/software/__init__.py b/misoclib/com/liteusb/software/__init__.py
new file mode 100644
index 00000000..e69de29b
diff --git a/misoclib/com/liteusb/software/ftdi/__init__.py b/misoclib/com/liteusb/software/ftdi/__init__.py
index 49b68af2..a9327fe1 100644
--- a/misoclib/com/liteusb/software/ftdi/__init__.py
+++ b/misoclib/com/liteusb/software/ftdi/__init__.py
@@ -5,13 +5,10 @@ import time
 import queue
 import threading
 
-_lpath = (os.path.dirname(__file__))
-if _lpath == '':
-    _lpath = '.'
 if platform.system() == "Windows":
-    libftdicom =  ctypes.cdll.LoadLibrary(_lpath + "/libftdicom.dll")
+    libftdicom =  ctypes.cdll.LoadLibrary("./libftdicom.dll")
 else:
-    libftdicom =  ctypes.cdll.LoadLibrary(_lpath + "/libftdicom.so")
+    libftdicom =  ctypes.cdll.LoadLibrary("./libftdicom.so")
 
 
 class FTDI_Device(ctypes.Structure):
diff --git a/misoclib/tools/litescope/software/driver/usb.py b/misoclib/tools/litescope/software/driver/usb.py
new file mode 100644
index 00000000..3416977f
--- /dev/null
+++ b/misoclib/tools/litescope/software/driver/usb.py
@@ -0,0 +1,71 @@
+from misoclib.com.liteusb.software.ftdi import FTDIComDevice
+
+class LiteScopeUSB2WishboneFTDIDriver:
+    cmds = {
+        "write": 0x01,
+        "read":  0x02
+    }
+    def __init__(self, interface, mode, tag, addrmap=None, debug=False):
+        self.interface = interface
+        self.mode = mode
+        self.tag = tag
+        self.debug = debug
+        self.com = FTDIComDevice(self.interface,
+                                 mode=mode,
+                                 uart_tag=tag,
+                                 dma_tag=16, # XXX FIXME
+                                 verbose=debug)
+        if addrmap is not None:
+            self.regs = build_map(addrmap, busword, self.read, self.write)
+
+    def open(self):
+        self.com.open()
+
+    def close(self):
+        self.com.close()
+
+    # XXX regroup cmds in a single packet
+    def read(self, addr, burst_length=1):
+        datas = []
+        self.com.uartflush()
+        self.com.uartwrite(self.cmds["read"])
+        self.com.uartwrite(burst_length)
+        word_addr = addr//4
+        self.com.uartwrite((word_addr >> 24) & 0xff)
+        self.com.uartwrite((word_addr >> 16) & 0xff)
+        self.com.uartwrite((word_addr >> 8) & 0xff)
+        self.com.uartwrite((word_addr >> 0) & 0xff)
+        for i in range(burst_length):
+            data = 0
+            for k in range(4):
+                data = data << 8
+                data |= self.com.uartread()
+            if self.debug:
+                print("RD {:08X} @ {:08X}".format(data, addr + 4*i))
+            datas.append(data)
+        if burst_length == 1:
+            return datas[0]
+        else:
+            return datas
+
+    # XXX regroup cmds in a single packet
+    def write(self, addr, data):
+        if isinstance(data, list):
+            burst_length = len(data)
+        else:
+            burst_length = 1
+            data = [data]
+        self.com.uartwrite(self.cmds["write"])
+        self.com.uartwrite(burst_length)
+        word_addr = addr//4
+        self.com.uartwrite((word_addr >> 24) & 0xff)
+        self.com.uartwrite((word_addr >> 16) & 0xff)
+        self.com.uartwrite((word_addr >> 8) & 0xff)
+        self.com.uartwrite((word_addr >> 0) & 0xff)
+        for i in range(len(data)):
+            dat = data[i]
+            for j in range(4):
+                self.com.uartwrite((dat >> 24) & 0xff)
+                dat = dat << 8
+            if self.debug:
+                print("WR {:08X} @ {:08X}".format(data[i], addr + 4*i))