From: lkcl <lkcl@web>
Date: Fri, 8 Oct 2021 23:49:01 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3692
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e70fdbb33ec6fef3afe35962166818216033bf2;p=libreriscv.git

---

diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn
index 17d6470dd..ece59c9db 100644
--- a/3d_gpu/architecture/dynamic_simd.mdwn
+++ b/3d_gpu/architecture/dynamic_simd.mdwn
@@ -276,7 +276,7 @@ be required** because dsl.Module is *already* 99% abstracted in terms
 of the lower-level Type 1 (ast.*) constructs.
 
 Analysis of the internals of nmigen shows that m.If, m.Else, m.FSM and m.Switch are all redirected to ast.py `Switch`.  Within that ast.Switch
-function only asy.Mux and other Type 1 (AST) "global" functions
+function only ast.Mux and other Type 1 (AST) "global" functions
 similar to python operator are used.  The hypothesis is therefore proposed that if `Value.mux` is added in an identical way to how `operator.add` calls `__add__` this may turn out to be all that (or most of what) is needed.
 
 <https://github.com/nmigen/nmigen/blob/59ef6e6a1c4e389a41148554f2dd492328820ecd/nmigen/hdl/dsl.py#L447>