From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 2 Dec 2018 07:44:59 +0000 (+0000)
Subject: add reg rename page
X-Git-Tag: convert-csv-opcode-to-binary~4824
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e77a9b4a09588488a8478447fce47f1e5e45a81;p=libreriscv.git

add reg rename page
---

diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn
index a1d003763..0387e5563 100644
--- a/3d_gpu/microarchitecture.mdwn
+++ b/3d_gpu/microarchitecture.mdwn
@@ -111,6 +111,8 @@ called the flip-flops orchestrating the timing "collectors".
 
 * <https://en.wikipedia.org/wiki/Tomasulo_algorithm>
 * <https://en.wikipedia.org/wiki/Reservation_station>
+* <https://en.wikipedia.org/wiki/Register_renaming> points out that
+  reservation stations take a *lot* of power.
 * Register File Bank Cacheing <https://www.princeton.edu/~rblee/ELE572Papers/MultiBankRegFile_ISCA2000.pdf>
 * Discussion <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2018-November/000157.html>
 * <https://github.com/UCSBarchlab/PyRTL/blob/master/examples/example5-instrospection.py>