From: Jacob Lifshay <programmerjake@gmail.com>
Date: Sat, 22 Oct 2022 00:46:58 +0000 (-0700)
Subject: fix get_masked_reg and add test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e79763394241cfcc2429d7be349d86be177448d;p=openpower-isa.git

fix get_masked_reg and add test
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 1aae2e60..92c76106 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -92,16 +92,16 @@ fregs = ['FRA', 'FRB', 'FRC', 'FRS', 'FRT']
 
 def get_masked_reg(regs, base, offs, ew_bits):
     # rrrright.  start by breaking down into row/col, based on elwidth
-    gpr_offs = offs // (64//ew_bits)
-    gpr_col = offs % (64//ew_bits)
+    gpr_offs = offs // (64 // ew_bits)
+    gpr_col = offs % (64 // ew_bits)
     # compute the mask based on ew_bits
-    mask = (1 << ew_bits)-1
+    mask = (1 << ew_bits) - 1
     # now select the 64-bit register, but get its value (easier)
-    val = regs[base+gpr_offs]
-    # now mask out the bit we don't want
-    val = val & ~(mask << (gpr_col*ew_bits))
-    # then return the bits we want, shifted down
-    return val >> (gpr_col*ew_bits)
+    val = regs[base + gpr_offs]
+    # shift down so element we want is at LSB
+    val >>= gpr_col * ew_bits
+    # mask so we only return the LSB element
+    return val & mask
 
 
 def set_masked_reg(regs, base, offs, ew_bits, value):
diff --git a/src/openpower/decoder/isa/test_caller.py b/src/openpower/decoder/isa/test_caller.py
index 5e8ad9c4..48355d78 100644
--- a/src/openpower/decoder/isa/test_caller.py
+++ b/src/openpower/decoder/isa/test_caller.py
@@ -1,6 +1,7 @@
 import unittest
 
 from nmutil.formaltest import FHDLTestCase
+from openpower.decoder.isa.caller import get_masked_reg, set_masked_reg
 from openpower.decoder.isa.test_runner import run_tst
 from openpower.decoder.selectable_int import SelectableInt
 from openpower.simulator.program import Program
@@ -254,5 +255,19 @@ class DecoderTestCase(FHDLTestCase):
         return simulator
 
 
+class TestGetSetMaskedReg(FHDLTestCase):
+    def test_get_set_masked_reg(self):
+        regs = [0x123456789abcdef, 0xfedcba9876543210,
+                0x2468ace13579bdf, 0xfdb975310eca8642]
+        set_masked_reg(regs, base=2, offs=5, ew_bits=16, value=0x369c)
+        self.assertEqual(list(map(hex, regs)), [
+            "0x123456789abcdef", "0xfedcba9876543210",
+            "0x2468ace13579bdf", "0xfdb97531369c8642"])
+        self.assertEqual(hex(get_masked_reg(regs, base=2, offs=5, ew_bits=16)),
+                         "0x369c")
+        self.assertEqual(hex(get_masked_reg(regs, base=2, offs=0, ew_bits=16)),
+                         "0x9bdf")
+
+
 if __name__ == "__main__":
     unittest.main()