From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 30 Jul 2018 09:06:20 +0000 (+0100)
Subject: add iocell peripheral and jtag pins
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e86087b1511a97e3e8a42a6577fd321bc52e3b6;p=pinmux.git

add iocell peripheral and jtag pins
---

diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv
index da213b7..dbe9f7e 100644
--- a/src/bsv/bsv_lib/soc_template.bsv
+++ b/src/bsv/bsv_lib/soc_template.bsv
@@ -313,7 +313,9 @@ package socgen;
           interface master=fabric.v_to_slaves
                                 [fromInteger(valueOf(Sdram_slave_num))];
         `endif
-        interface slow_ios=slow_peripherals.slow_ios;
+        interface slow_ios = slow_peripherals.slow_ios;
+        interface iocell_side = slow_peripherals.iocell_side;
+
 {6}
     endmodule
 endpackage
diff --git a/src/bsv/peripheral_gen/jtag.py b/src/bsv/peripheral_gen/jtag.py
index 2016b0b..c0891fd 100644
--- a/src/bsv/peripheral_gen/jtag.py
+++ b/src/bsv/peripheral_gen/jtag.py
@@ -13,6 +13,19 @@ class jtag(PBase):
         # YUK!
         return "interface Ifc_jtagdtm jtag{0}_out;".format(count)
 
+    def get_clock_reset(self, name, count):
+        return "tck, trst"
+
+    def pinname_in(self, pname):
+        return {'tms': 'tms',
+                'tdi': 'tdi',
+                }.get(pname, '')
+
+    def pinname_out(self, pname):
+        return {'tck': 'tck',
+                'tdo': 'tdo',
+                }.get(pname, '')
+
     def mkfast_peripheral(self):
         return """\
 Ifc_jtagdtm jtag{0} <-mkjtagdtm(clocked_by tck, reset_by trst);