From: Jacob Lifshay Date: Tue, 7 Mar 2023 04:40:00 +0000 (-0800) Subject: fix formatting X-Git-Tag: opf_rfc_ls001_v3~193 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e87a139faa7a11d0663f393e73eb66ec54e7102;p=libreriscv.git fix formatting --- diff --git a/openpower/sv/int_fp_mv_reduced_insn_count.mdwn b/openpower/sv/int_fp_mv_reduced_insn_count.mdwn index 3b63343a3..efe56a56b 100644 --- a/openpower/sv/int_fp_mv_reduced_insn_count.mdwn +++ b/openpower/sv/int_fp_mv_reduced_insn_count.mdwn @@ -1,5 +1,7 @@ [[!tag standards]] +# Reduced Instruction List Attempt + Attempt at [reducing the number of different instructions](#reduced-instruction-list) used for int/fp moves. IMPORTANT: don't merge until everyone's had a chance to review it. @@ -31,14 +33,12 @@ IMPORTANT: don't merge until everyone's had a chance to review it. | `fcvt[s]tg[u][w/d][.] RT, FRA, Mode` | `fcvttg RT, FRA, Mode, S_AND_RC, INT_MODE` | goes against PowerISA naming scheme | Notes: + * PowerISA uses `s` and `.` suffixes instead of an immediate for Single and Rc=1 modes respectively. * PowerISA uses `w`, `uw`, `d`, and `ud` suffixes instead of an immediate for selecting between unsigned/signed 32-bit/64-bit. - -About the only operations we can realistically remove are Rc=1 versions, however imho that isn't necessary. - -Realistically we can't remove any of the Rc=0 instructions because it would make the instruction set non-orthogonal and it would penalize the code using those operations, almost all of which are quite common. - -Attempting to condense them into 6 instructions by undoing the PowerISA naming scheme works, but all that changed is the assembler mnemonics (in a bad way by being inconsistent with PowerISA), the instruction encodings don't change at all, unless we want to use an expanded opcode. +* About the only operations we can realistically remove are Rc=1 versions, however Jacob thinks that isn't necessary. +* Realistically we can't remove any of the Rc=0 instructions because it would make the instruction set non-orthogonal and it would penalize the code using those operations, almost all of which are quite common. +* Attempting to condense them into 6 instructions by undoing the PowerISA naming scheme works, but all that changed is the assembler mnemonics (in a bad way by being inconsistent with PowerISA), the instruction encodings don't change at all, unless we want to use an expanded opcode. # Rest of document not yet modified: