From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Wed, 7 Aug 2019 17:14:45 +0000 (-0700)
Subject: Merge branch 'master' into firrtl_err_on_unsupported_cell
X-Git-Tag: working-ls180~1153^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e8a98c8fd5f31b514748676804dd1237bce4225;p=yosys.git

Merge branch 'master' into firrtl_err_on_unsupported_cell

# Conflicts:
#	backends/firrtl/firrtl.cc
---

5e8a98c8fd5f31b514748676804dd1237bce4225
diff --cc backends/firrtl/firrtl.cc
index b7a798b85,9ef6e311a..ad4b37353
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@@ -831,9 -927,23 +927,23 @@@ struct FirrtlWorke
  				}
  				cell_exprs.push_back(stringf("    %s <= %s\n", y_id.c_str(), expr.c_str()));
  				register_reverse_wire_map(y_id, cell->getPort("\\Y"));
+ 				continue;
+ 			}
+ 			if (cell->type == "$pos") {
+ 				// assign y = a;
+ //				printCell(cell);
+ 				string a_expr = make_expr(cell->getPort("\\A"));
+ 				// Verilog appears to treat the result as signed, so if the result is wider than "A",
+ 				//  we need to pad.
+ 				if (a_width < y_width) {
+ 					a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
+ 				}
+ 				wire_decls.push_back(stringf("    wire %s: UInt<%d>\n", y_id.c_str(), y_width));
+ 				cell_exprs.push_back(stringf("    %s <= %s\n", y_id.c_str(), a_expr.c_str()));
+ 				register_reverse_wire_map(y_id, cell->getPort("\\Y"));
  				continue;
  			}
 -			log_warning("Cell type not supported: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
 +			log_error("Cell type not supported: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
  		}
  
  		for (auto conn : module->connections())