From: R Veera Kumar <vklr@vkten.in>
Date: Tue, 9 Nov 2021 13:53:46 +0000 (+0530)
Subject: Add expected state to case_1_regression for extsw for alu_cases unit test
X-Git-Tag: sv_maxu_works-initial~764
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e8f8402f6d6ec8a251803d619e10106cb8359b3;p=openpower-isa.git

Add expected state to case_1_regression for extsw for alu_cases unit test
---

diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py
index 13efdd53..f166308e 100644
--- a/src/openpower/test/alu/alu_cases.py
+++ b/src/openpower/test/alu/alu_cases.py
@@ -15,7 +15,10 @@ class ALUTestCase(TestAccumulatorBase):
         lst = [f"extsw 3, 1"]
         initial_regs = [0] * 32
         initial_regs[1] = 0xb6a1fc6c8576af91
-        self.add_case(Program(lst, bigendian), initial_regs)
+        e = ExpectedState(pc=4)
+        e.intregs[1] = 0xb6a1fc6c8576af91
+        e.intregs[3] = 0xffffffff8576af91
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
         lst = [f"subf 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 0x3d7f3f7ca24bac7b