From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 3 Dec 2018 11:08:34 +0000 (+0000)
Subject: add links
X-Git-Tag: convert-csv-opcode-to-binary~4819
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5eb1d608a7932e9f9619301688c15f4c91bd8145;p=libreriscv.git

add links
---

diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn
index cab0d2deb..bd5a0ac87 100644
--- a/3d_gpu/microarchitecture.mdwn
+++ b/3d_gpu/microarchitecture.mdwn
@@ -120,6 +120,7 @@ called the flip-flops orchestrating the timing "collectors".
 * <https://github.com/ssc3?tab=repositories> interesting stuff
 * <https://en.wikipedia.org/wiki/Classic_RISC_pipeline#Solution_A._Bypassing>
   pipeline bypassing
+* <http://ece-research.unm.edu/jimp/611/slides/chap4_7.html> Tomasulo / Reorder
 * Register File Bank Cacheing <https://www.princeton.edu/~rblee/ELE572Papers/MultiBankRegFile_ISCA2000.pdf>
 * Discussion <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2018-November/000157.html>
 * <https://github.com/UCSBarchlab/PyRTL/blob/master/examples/example5-instrospection.py>