From: Gabe Black Date: Mon, 18 May 2020 13:10:15 +0000 (-0700) Subject: fastmodel: Add an ISA class which defers to IRIS. X-Git-Tag: v20.1.0.0~45 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5eb3e44f5478c543015131d18e61947a188c06b1;p=gem5.git fastmodel: Add an ISA class which defers to IRIS. This class is just to enable checkpointing of "ISA" state, aka the MiscRegs. Change-Id: I45315b8aaa09aaf6230f44665c13597400efd780 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29822 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py index 9ac3f400b..65d57a1c1 100644 --- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py +++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py @@ -42,9 +42,6 @@ class FastModelCortexA76(IrisBaseCPU): cntfrq = Param.UInt64(0x1800000, "Value for the CNTFRQ timer register") - # We shouldn't need these, but gem5 gets mad without them. - isa = [ ArmISA() ] - evs = Parent.evs redistributor = Gicv3CommsTargetSocket('GIC communication target') diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc b/src/arch/arm/fastmodel/CortexA76/thread_context.cc index 1b0ce14da..1259bf166 100644 --- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc +++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc @@ -35,11 +35,11 @@ namespace FastModel { -CortexA76TC::CortexA76TC( - ::BaseCPU *cpu, int id, System *system, ::BaseTLB *dtb, ::BaseTLB *itb, +CortexA76TC::CortexA76TC(::BaseCPU *cpu, int id, System *system, + ::BaseTLB *dtb, ::BaseTLB *itb, ::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path) : - ThreadContext(cpu, id, system, dtb, itb, iris_if, iris_path) + ThreadContext(cpu, id, system, dtb, itb, isa, iris_if, iris_path) {} bool diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.hh b/src/arch/arm/fastmodel/CortexA76/thread_context.hh index 344a508a4..db848db5a 100644 --- a/src/arch/arm/fastmodel/CortexA76/thread_context.hh +++ b/src/arch/arm/fastmodel/CortexA76/thread_context.hh @@ -48,7 +48,7 @@ class CortexA76TC : public Iris::ThreadContext public: CortexA76TC(::BaseCPU *cpu, int id, System *system, - ::BaseTLB *dtb, ::BaseTLB *itb, + ::BaseTLB *dtb, ::BaseTLB *itb, ::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path); diff --git a/src/arch/arm/fastmodel/iris/Iris.py b/src/arch/arm/fastmodel/iris/Iris.py index 3531b85c7..a73e46ea3 100644 --- a/src/arch/arm/fastmodel/iris/Iris.py +++ b/src/arch/arm/fastmodel/iris/Iris.py @@ -28,6 +28,7 @@ from m5.proxy import * from m5.objects.BaseCPU import BaseCPU from m5.objects.BaseInterrupts import BaseInterrupts +from m5.objects.BaseISA import BaseISA from m5.objects.BaseTLB import BaseTLB class IrisTLB(BaseTLB): @@ -40,6 +41,11 @@ class IrisInterrupts(BaseInterrupts): cxx_class = 'Iris::Interrupts' cxx_header = 'arch/arm/fastmodel/iris/interrupts.hh' +class IrisISA(BaseISA): + type = 'IrisISA' + cxx_class = 'Iris::ISA' + cxx_header = 'arch/arm/fastmodel/iris/isa.hh' + class IrisBaseCPU(BaseCPU): type = 'IrisBaseCPU' abstract = True @@ -67,5 +73,11 @@ class IrisBaseCPU(BaseCPU): dtb = IrisTLB() itb = IrisTLB() + def createThreads(self): + if len(self.isa) == 0: + self.isa = [ IrisISA() for i in range(self.numThreads) ] + else: + assert(len(self.isa) == int(self.numThreads)) + def createInterruptController(self): self.interrupts = [ IrisInterrupts() for i in range(self.numThreads) ] diff --git a/src/arch/arm/fastmodel/iris/SConscript b/src/arch/arm/fastmodel/iris/SConscript index af3abe8d6..9586f0fca 100644 --- a/src/arch/arm/fastmodel/iris/SConscript +++ b/src/arch/arm/fastmodel/iris/SConscript @@ -31,6 +31,7 @@ if not env['USE_ARM_FASTMODEL']: SimObject('Iris.py') Source('cpu.cc') Source('interrupts.cc') +Source('isa.cc') Source('tlb.cc') Source('thread_context.cc') diff --git a/src/arch/arm/fastmodel/iris/cpu.hh b/src/arch/arm/fastmodel/iris/cpu.hh index 3660dd38c..b0ba2c1ec 100644 --- a/src/arch/arm/fastmodel/iris/cpu.hh +++ b/src/arch/arm/fastmodel/iris/cpu.hh @@ -137,8 +137,9 @@ class CPU : public Iris::BaseCPU int thread_id = 0; for (const std::string &sub_path: params->thread_paths) { std::string path = parent_path + "." + sub_path; - auto *tc = new TC(this, thread_id++, sys, - params->dtb, params->itb,iris_if, path); + auto id = thread_id++; + auto *tc = new TC(this, id, sys, params->dtb, params->itb, + params->isa[id], iris_if, path); threadContexts.push_back(tc); } } diff --git a/src/arch/arm/fastmodel/iris/isa.cc b/src/arch/arm/fastmodel/iris/isa.cc new file mode 100644 index 000000000..19b0d16e8 --- /dev/null +++ b/src/arch/arm/fastmodel/iris/isa.cc @@ -0,0 +1,48 @@ +/* + * Copyright 2020 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "arch/arm/fastmodel/iris/isa.hh" + +#include "arch/arm/miscregs.hh" +#include "cpu/thread_context.hh" +#include "params/IrisISA.hh" +#include "sim/serialize.hh" + +void +Iris::ISA::serialize(CheckpointOut &cp) const +{ + RegVal miscRegs[ArmISA::NUM_PHYS_MISCREGS]; + for (int i = 0; i < ArmISA::NUM_PHYS_MISCREGS; i++) + miscRegs[i] = tc->readMiscRegNoEffect(i); + SERIALIZE_ARRAY(miscRegs, ArmISA::NUM_PHYS_MISCREGS); +} + +Iris::ISA * +IrisISAParams::create() +{ + return new Iris::ISA(this); +} diff --git a/src/arch/arm/fastmodel/iris/isa.hh b/src/arch/arm/fastmodel/iris/isa.hh new file mode 100644 index 000000000..72f2c1c79 --- /dev/null +++ b/src/arch/arm/fastmodel/iris/isa.hh @@ -0,0 +1,46 @@ +/* + * Copyright 2019 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__ +#define __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__ + +#include "arch/generic/isa.hh" + +namespace Iris +{ + +class ISA : public BaseISA +{ + public: + ISA(const Params *p) : BaseISA(p) {} + + void serialize(CheckpointOut &cp) const; +}; + +} // namespace Iris + +#endif // __ARCH_ARM_FASTMODEL_IRIS_ISA_HH__ diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc b/src/arch/arm/fastmodel/iris/thread_context.cc index 070a3862f..027006e5a 100644 --- a/src/arch/arm/fastmodel/iris/thread_context.cc +++ b/src/arch/arm/fastmodel/iris/thread_context.cc @@ -305,8 +305,9 @@ ThreadContext::semihostingEvent( ThreadContext::ThreadContext( BaseCPU *cpu, int id, System *system, ::BaseTLB *dtb, ::BaseTLB *itb, - iris::IrisConnectionInterface *iris_if, const std::string &iris_path) : - _cpu(cpu), _threadId(id), _system(system), _dtb(dtb), _itb(itb), + BaseISA *isa, iris::IrisConnectionInterface *iris_if, + const std::string &iris_path) : + _cpu(cpu), _threadId(id), _system(system), _dtb(dtb), _itb(itb), _isa(isa), _irisPath(iris_path), vecRegs(ArmISA::NumVecRegs), vecPredRegs(ArmISA::NumVecPredRegs), comInstEventQueue("instruction-based event queue"), diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh b/src/arch/arm/fastmodel/iris/thread_context.hh index dc5396952..a37fbc6e2 100644 --- a/src/arch/arm/fastmodel/iris/thread_context.hh +++ b/src/arch/arm/fastmodel/iris/thread_context.hh @@ -59,6 +59,7 @@ class ThreadContext : public ::ThreadContext System *_system; ::BaseTLB *_dtb; ::BaseTLB *_itb; + ::BaseISA *_isa; std::string _irisPath; iris::InstanceId _instId = iris::IRIS_UINT64_MAX; @@ -167,7 +168,7 @@ class ThreadContext : public ::ThreadContext public: ThreadContext(::BaseCPU *cpu, int id, System *system, - ::BaseTLB *dtb, ::BaseTLB *itb, + ::BaseTLB *dtb, ::BaseTLB *itb, ::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path); virtual ~ThreadContext(); @@ -213,7 +214,7 @@ class ThreadContext : public ::ThreadContext BaseISA * getIsaPtr() override { - panic("%s not implemented.", __FUNCTION__); + return _isa; } PortProxy &getPhysProxy() override { return *physProxy; }