From: klehman <klehman9@comcast.net>
Date: Wed, 8 Sep 2021 13:03:13 +0000 (-0400)
Subject: initial commit of sim state class
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5eb5477aef6abae55dde17cc5d5f182b32bda10b;p=soc.git

initial commit of sim state class
---

diff --git a/src/soc/simple/test/teststate.py b/src/soc/simple/test/teststate.py
new file mode 100644
index 00000000..0520d166
--- /dev/null
+++ b/src/soc/simple/test/teststate.py
@@ -0,0 +1,11 @@
+class SimState:
+    def __init__(self, sim):
+        self.sim = sim
+
+    def get_intregs(self):
+        self.intregs = []
+        for i in range(32):
+            simregval = self.sim.gpr[i].asint()
+            self.intregs.append(simregval)
+
+# HDL class here with same functions