From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 5 Apr 2023 10:17:20 +0000 (+0100)
Subject: add future potential section on DD-FF-Rc=1
X-Git-Tag: opf_rfc_ls012_v1~120
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5ebe43c1738c778ffa262e2ff7273b7dcf687adc;p=libreriscv.git

add future potential section on DD-FF-Rc=1
---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index cb26ac0cf..d2747b2db 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -513,6 +513,15 @@ the pairs, and consequently allowing Vectorised Data-Dependent Fail-First is
 useful.  Care should be taken however when VL is truncated in Vertical-First
 Mode.
 
+**Future potential**
+
+Although Rc=1 on LD/ST is a rare occurrence at present, future versions
+of Power ISA *might* conceivably have Rc=1 LD/ST Scalar instructions, and
+with the SVP64 Vectorisation Prefixing being itself a RISC-paradigm that
+is itself fully-independent of the Scalar Suffix Defined Words, prohibiting
+Rc=1 Data-Dependent Mode on future potential LD/ST operations is not
+strategically sound.
+
 ## LOAD/STORE Elwidths <a name="elwidth"></a>
 
 Loads and Stores are almost unique in that the Power Scalar ISA