From: lkcl <lkcl@web>
Date: Wed, 8 Jun 2022 15:13:51 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1910^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5ebeb2c0fa737e7bd7d307ba2886b36684fffde3;p=libreriscv.git

---

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index b09bc74d2..7ae59c950 100644
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -98,3 +98,9 @@ must also be supported (sz, dz) however
 all other Modes (Saturation, Fail-First, Predicate-Result,
 Iteration/Reduction) are entirely optional. Implementation of Element-Width
 Overrides is also optional.
+
+One of the important side-benefits of this SV Compliancy Level is that it
+brings Hardware-level support for Predication to the entire Scalar Power
+ISA, completely without
+modifying the Scalar Power ISA.  The cost is that instructions are Prefixed
+to 64-bit.