From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 19:41:11 +0000 (-0700)
Subject: Remove -icells
X-Git-Tag: working-ls180~881^2^2~231
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5eda5fc7eb889b738739270f67349b1027951443;p=yosys.git

Remove -icells
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 3525e4de9..d4874af45 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -230,9 +230,9 @@ struct SynthXilinxPass : public ScriptPass
 	{
 		if (check_label("begin")) {
 			if (vpr)
-				run("read_verilog -lib -icells -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+				run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 			else
-				run("read_verilog -lib -icells +/xilinx/cells_sim.v");
+				run("read_verilog -lib +/xilinx/cells_sim.v");
 
 			run("read_verilog -lib +/xilinx/cells_xtra.v");